# US 12,003,234 B2 · Bootstrapped switch > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,003,234 B2 - Document ID: US12003234B2 - Status: Granted - Kind: B2 - Application number: 18/098,132 - Filed: 2023-01-18 - Published: 2023-08-24 - Granted: 2024-06-04 - Earliest claimed: 2022-02-22 - Assignees: Realtek Semiconductor Corp. - Applicants: Realtek Semiconductor Corporation - Inventors: Liang-Huan Lei - Web page: https://patentgrep.com/patent/US12003234B2 ## CPC - H03K 17/145: {in field-effect transistor switches} - H03K 17/6872: {using complementary field-effect transistors} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A bootstrapped switch includes a sampling transistor, a bootstrapped circuit, and a buffer circuit. The sampling transistor is configured to be selectively turned on according to a level of a control node, in order to transmit an input signal from a first terminal of the sampling transistor to a second terminal of the sampling transistor, in which a body of the sampling transistor is configured to receive a buffer signal. The bootstrapped circuit is configured to pull up the level of the control node, such that a constant voltage difference is present between the control node and the first terminal of the sampling transistor during a turn-on interval of the sampling transistor. The buffer circuit is configured to generate the buffer signal according to the input signal. ## Claims ### Claim 1 A bootstrapped switch, comprising: a sampling transistor configured to be selectively turned on according to a level of a control node, in order to transmit an input signal from a first terminal of the sampling transistor to a second terminal of the sampling transistor, wherein a body of the sampling transistor is configured to receive a buffer signal; a bootstrapped circuit configured to pull up the level of the control node, such that a constant voltage difference is present between the control node and the first terminal of the sampling transistor during a turn-on interval of the sampling transistor; and a buffer circuit configured to generate the buffer signal according to the input signal, wherein the bootstrapped circuit comprises a plurality of N-type transistors, a body of at least one of the plurality of N-type transistors is configured to receive the buffer signal, and the at least one of the plurality of N-type transistors is turned on and receives the input signal during the turn-on interval of the sampling transistor. ### Claim 2 (depends on 1) The bootstrapped switch of claim 1, wherein a body of at least one transistor in the plurality of N-type transistors does not receive the buffer signal and is coupled to a source of the at least one transistor. ### Claim 3 (depends on 1) The bootstrapped switch of claim 1, wherein the body of the at least one of the plurality of N-type transistors does not directly receive the input signal. ### Claim 4 (depends on 3) The bootstrapped switch of claim 3, wherein the at least one of the plurality of N-type transistors is turned on and receives the input signal during the turn-on interval of the sampling transistor. ### Claim 5 (depends on 1) The bootstrapped switch of claim 1, wherein the bootstrapped circuit further comprises: a capacitor, wherein two terminals of the capacitor are coupled to a first node and a second node, respectively; a first P-type transistor configured to be selectively turned on according to a level of a third node, in order to couple the second node to the control node; a second P-type transistor configured to be selectively turned on according to the level of the control node, in order to transmit a supply voltage to the second node; and a third P-type transistor configured to be selectively turned on according to a third clock signal, in order to transmit the supply voltage to the third node, and wherein the plurality of N-type transistors comprise: a first N-type transistor configured to be selectively turned on according to the level of the control node, in order to couple the first terminal of the sampling transistor to the first node; a second N-type transistor configured to be selectively turned on according to a first clock signal, in order to couple the first node to ground; a third N-type transistor configured to be selectively turned on according to a second clock signal, in order to couple the first node to the third node; and a fourth N-type transistor configured to be selectively turned on according to the level of the control node, in order to couple the first node to the third node. ### Claim 6 (depends on 5) The bootstrapped switch of claim 5, wherein the second N-type transistor is not turned on during the turn-on interval of the sampling transistor. ### Claim 7 (depends on 5) The bootstrapped switch of claim 5, further comprising: a fifth N-type transistor configured to be turned on according to the supply voltage; and a sixth N-type transistor configured to be selectively turned on according to the first clock signal, in order to couple the control node to ground via the fifth N-type transistor. ### Claim 8 (depends on 1) The bootstrapped switch of claim 1, wherein the body of the sampling transistor receives the buffer signal to reduce a variation of a capacitance value of a parasitic capacitor of the sampling transistor, and the parasitic capacitor is voltage dependent. ### Claim 9 A bootstrapped switch, comprising: a sampling transistor configured to be selectively turned on according to a level of a control node, in order to transmit an input signal from a first terminal of the sampling transistor to a second terminal of the sampling transistor; a bootstrapped circuit configured to pull up the level of the control node, such that a constant voltage difference is present between the control node and the first terminal of the sampling transistor during a turn-on interval of the sampling transistor, wherein a body of at least one transistor in a plurality of N-type transistors of the bootstrapped circuit is configured to receive a buffer signal, and the plurality of N-type transistors are turned on and receive the input signal during the turn-on interval of the sampling transistor; and a buffer circuit configured to generate the buffer signal according to the input signal. ### Claim 10 (depends on 9) The bootstrapped switch of claim 9, wherein a body of a first transistor in the plurality of N-type transistors does not receive the buffer signal and is coupled to a source of the first transistor. ### Claim 11 (depends on 9) The bootstrapped switch of claim 9, wherein a body of the sampling transistor is coupled to a source of the sampling transistor. ### Claim 12 A bootstrapped switch, comprising: a sampling transistor configured to be selectively turned on according to a level of a control node, in order to transmit an input signal from a first terminal of the sampling transistor to a second terminal of the sampling transistor, wherein a body of the sampling transistor is configured to receive a buffer signal; a bootstrapped circuit configured to pull up the level of the control node, such that a constant voltage difference is present between the control node and the first terminal of the sampling transistor during a turn-on interval of the sampling transistor; and a buffer circuit configured to generate the buffer signal according to the input signal, wherein the bootstrapped circuit comprises a plurality of N-type transistors, a body of at least one first transistor of the plurality of N-type transistors is configured to receive the buffer signal, and a body of at least one second transistor in the plurality of N-type transistors does not receive the buffer signal and is coupled to a source of the at least one second transistor.