# US 12,003,233 B1 · High bandwidth integrated multiplexer and driver stage for transmitter

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- Number: US 12,003,233 B1
- Document ID: US12003233B1
- Status: Granted
- Kind: B1
- Application number: 18/050,822
- Filed: 2022-10-28
- Granted: 2024-06-04
- Earliest claimed: 2022-10-28
- Assignees: Synopsys, Inc.
- Applicants: Synopsys, Inc.
- Inventors: Varun Kant Tripathi; Shourya Kansal
- Web page: https://patentgrep.com/patent/US12003233B1

## CPC

- H03K 17/6872: {using complementary field-effect transistors}
- G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom
- H03K 17/005: {with several inputs only}
- H03K 17/693: Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00)
- H03K 19/0175: Coupling arrangements; Interface arrangements (interface arrangements for digital computers G06F3/00, G06F13/00)
- H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence)
- H04B 1/04: Circuits
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04B: TRANSMISSION

## Abstract

A system for serializing data includes, in part, serialization circuitry configured to convert input data provided through parallel input streams into a lesser number of parallel output streams. The input data is converted through sampling based on a set of clock signals that are phase-offset. The system further includes a pre-driver circuit having combinational logic including a first multiplexer. The first multiplexer is configured to generate an output of the pre-driver circuit through combining the converted input data such that the number of parallel output streams is reduced. The system further includes a driver circuit configured to generate, using the output of the pre-driver circuit, a final output stream corresponding to the input data in serial format. The driver circuit is integrated with a second multiplexer, with the output of the pre-driver circuit operating as both control input and data input to the second multiplexer.

## Claims

### Claim 1

A system comprising:
a clock source configured to generate a set of clock signals that are phase-offset;
serialization circuitry configured to convert input data provided through parallel input streams into a lesser number of parallel output streams, whereto to convert the input data, the serialization circuitry samples the input data using the clock signals;
a pre-driver circuit comprising combinational logic including a first multiplexer, wherein the first multiplexer is configured to generate an output of the pre-driver circuit through combining the converted input data such that the lesser number of parallel output streams is further reduced; and
a driver circuit configured to generate, using the output of the pre-driver circuit, a final output stream corresponding to the input data in serial format, wherein the driver circuit is integrated with a second multiplexer, and wherein the output of the pre-driver circuit operates as both control input and data input to the second multiplexer.

### Claim 2 (depends on 1)

The system of claim 1, wherein:
the driver circuit comprises a plurality of p-channel metal-oxide-semiconductor (PMOS) transistors and a plurality of n-channel metal-oxide-semiconductor (NMOS) transistors; and
the output of the pre-driver circuit forms gate inputs to the PMOS transistors and the NMOS transistors.

### Claim 3 (depends on 2)

The system of claim 2, wherein the combinational logic of the pre-driver circuit comprises:
a plurality of OR gates, each OR gate forming a gate input to a corresponding NMOS transistor; and
a plurality of AND gates, each AND gate forming a gate input to a corresponding PMOS transistor.

### Claim 4 (depends on 2)

The system of claim 2, wherein the final output stream is formed at a node where drain terminals of the PMOS transistors are connected to drain terminals of the NMOS transistors.

### Claim 5 (depends on 1)

The system of claim 1, wherein:
the serialization circuitry comprises a first set of logic gates, each logic gate in the first set of logic gates operating on a corresponding data input and a subset of the clock signals generated by the clock source; and
the combinational logic of the pre-driver circuit comprises a second set of logic gates, each logic gate in the second set of logic gates operating on outputs from two or more logic gates in the first set of logic gates.

### Claim 6 (depends on 5)

The system of claim 5, wherein the subset of clock signals on which a logic gate in the first set of logic gates operates is a pair of clock signals that are phase-offset by one unit interval.

### Claim 7 (depends on 1)

The system of claim 1, wherein the set of clock signals represents four phases of a clock operating at a frequency four times slower than a baud rate of the final output stream.

### Claim 8 (depends on 7)

The system of claim 7, wherein the first multiplexer generates the output of the pre-driver circuit at half the baud rate of the final output stream.

### Claim 9 (depends on 1)

The system of claim 1, wherein the first multiplexer is a 4:2 multiplexer, and wherein the second multiplexer is a 2:1 multiplexer.

### Claim 10 (depends on 1)

The system of claim 1, wherein the final output stream corresponds to an output of a transmitter in a Serializer-Deserializer (SerDes) interface.

### Claim 11

A method comprising:
obtaining a set of clock signals that are phase-offset;
converting input data provided through parallel input streams into a lesser number of parallel output streams, wherein the converting of the input data comprises sampling the input data using the clock signals;
generating, using combinational logic including a first multiplexer, an intermediate output through combining the converted input data such that the lesser number of parallel output streams is further reduced; and
generating, using a second multiplexer integrated with a driver circuit, a final output stream corresponding to the input data in serial format, wherein the intermediate output operates as both control input and data input to the second multiplexer.

### Claim 12 (depends on 11)

The method of claim 11, wherein:
the driver circuit comprises a plurality of p-channel metal-oxide-semiconductor (PMOS) transistors and a plurality of n-channel metal-oxide-semiconductor (NMOS) transistors; and
the intermediate output forms gate inputs to the PMOS transistors and the NMOS transistors.

### Claim 13 (depends on 12)

The method of claim 12, wherein the combinational logic comprises:
a plurality of OR gates, each OR gate forming a gate input to a corresponding NMOS transistor; and
a plurality of AND gates, each AND gate forming a gate input to a corresponding PMOS transistor.

### Claim 14 (depends on 12)

The method of claim 12, wherein the final output stream is formed at a node where drain terminals of the PMOS transistors are connected to drain terminals of the NMOS transistors.

### Claim 15 (depends on 11)

The method of claim 11, wherein:
the converting of the input data is performed using a first set of logic gates, each logic gate in the first set of logic gates operating on a corresponding data input and a subset of the clock signals; and
the generating of the intermediate output is performed using a second set of logic gates, each logic gate in the second set of logic gates operating on outputs from two or more logic gates in the first set of logic gates.

### Claim 16 (depends on 15)

The method of claim 15, wherein the subset of clock signals on which a logic gate in the first set of logic gates operates is a pair of clock signals that are phase-offset by one unit interval.

### Claim 17 (depends on 11)

The method of claim 11, wherein the set of clock signals represents four phases of a clock operating at a frequency four times slower than a baud rate of the final output stream.

### Claim 18 (depends on 17)

The method of claim 17, wherein the first multiplexer generates the intermediate output at half the baud rate of the final output stream.

### Claim 19 (depends on 11)

The method of claim 11, further comprising:
transmitting the final output stream to a receiver device through a Serializer-Deserializer (SerDes) interface.