# US 12,003,231 B2 · Double gate transistor device and method of operating > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,003,231 B2 - Document ID: US12003231B2 - Status: Granted - Kind: B2 - Application number: 16/722,809 - Filed: 2019-12-20 - Published: 2020-04-30 - Granted: 2024-06-04 - Earliest claimed: 2016-02-29 - Assignees: Infineon Technologies Austria AG - Applicants: Infineon Technologies Austria AG - Inventors: Markus Bina; Jens Barrenscheen; Anton Mauder - Web page: https://patentgrep.com/patent/US12003231B2 ## CPC - H03K 17/567: Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT - H03K 17/687: the devices being field-effect transistors - H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs} - H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs} - H10D 30/477: {Vertical HEMTs or vertical HHMTs} - H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)} - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 48/362: {Unipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunnelling transistors [RTT], bulk barrier transistors [BBT], planar doped barrier transistors [PDBT] or charge injection transistors [CHINT]} - H10D 62/165: {Tunnel injectors} - H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates} - H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)} - H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates} - H03K 2017/6878: {using multi-gate field-effect transistors} - H10D 62/343: {Gate regions of field-effect devices having PN junction gates} - H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract In accordance with an embodiment, a method includes switching on a transistor device by generating a first conducting channel by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel by driving a second gate electrode, wherein the second gate electrode is adjacent the first gate electrode in a current flow direction of the transistor device. ## Claims ### Claim 1 A transistor device comprising: a semiconductor body with a first semiconductor layer comprising a first type of group III nitride and a second semiconductor layer adjoining the first semiconductor layer and comprising a second type of group III nitride; a source electrode having a vertical edge immediately adjacent to a first vertical edge of the first semiconductor layer and immediately adjacent to a first vertical edge of the second semiconductor layer in a vertical cross-sectional view; a drain electrode spaced apart from the source electrode and having a vertical edge immediately adjacent to a second vertical edge of the first semiconductor layer and immediately adjacent to a second vertical edge of the second semiconductor layer in a vertical cross-sectional view; and a first gate electrode configured for generating a first conducting channel in the semiconductor body in response to a first signal driving the first gate electrode at a first slew rate and a second gate electrode configured for generating a second conducting channel in the semiconductor body in response to a second signal driving the second gate electrode at a second slew rate greater than the first slew rate, wherein the first gate electrode and the second gate electrode are spaced apart in a current flow direction of the transistor device, wherein the first gate electrode and the second gate electrode are electrically insulated with respect to each other, and wherein the first gate electrode and the second gate electrode are controlled individually with respect to each other in a mode of operation, wherein each of the first gate electrode and the second gate electrode extends through the second semiconductor layer into the first semiconductor layer and is dielectrically insulated from the second semiconductor layer and the first semiconductor layer by a gate dielectric. ### Claim 2 (depends on 1) The transistor device of claim 1, wherein the semiconductor body further comprises a third semiconductor layer adjoining the second semiconductor layer and comprising a group III nitride, and wherein each of the first gate electrode and the second gate electrode further extends through the third semiconductor layer and is further dielectrically insulated from the third semiconductor layer by the gate dielectric. ### Claim 3 (depends on 1) The transistor device of claim 1, wherein each of the first semiconductor layer and the second semiconductor layer comprises a doped semiconductor layer. ### Claim 4 (depends on 1) The transistor device of claim 1, wherein each of the first semiconductor layer and the second semiconductor layer comprises an intrinsic semiconductor layer. ### Claim 5 (depends on 4) The transistor device of claim 4, wherein the semiconductor body further comprises at least one third semiconductor layer adjoining the second semiconductor layer and comprising a doped group III nitride, and wherein each of the first gate electrode and the second gate electrode further extends through the at least one third semiconductor layer and is further dielectrically insulated from the at least one third semiconductor layer by the gate dielectric. ### Claim 6 (depends on 1) The transistor device of claim 1, further comprising a field electrode adjoining the second gate electrode. ### Claim 7 (depends on 1) The transistor device of claim 1, wherein the second gate electrode is electrically connected with the source electrode. ### Claim 8 (depends on 1) The transistor device of claim 1, wherein the first type of group III nitride comprises gallium nitride (GaN), and wherein the second type of group III nitride comprises aluminum gallium nitride (AlGaN). ### Claim 9 A method of using a transistor device, the method comprising: with a first gate electrode of the transistor device, generating a first conducting channel in a semiconductor body in response to a first signal driving the first gate electrode at a first slew rate, wherein the semiconductor body has a first semiconductor layer comprising a first type of group III nitride and a second semiconductor layer adjoining the first semiconductor layer and comprising a second type of group III nitride; and with a second gate electrode of the transistor device, generating a second conducting channel in the semiconductor body in response to a second signal driving the second gate electrode at a second slew rate greater than the first slew rate, wherein the first gate electrode and the second gate electrode are spaced apart in a current flow direction of the transistor device, wherein the first gate electrode and the second gate electrode are electrically insulated with respect to each other, and wherein the first gate electrode and the second gate electrode are controlled individually with respect to each other in a mode of operation, wherein each of the first gate electrode and the second gate electrode extends through the second semiconductor layer into the first semiconductor layer and is dielectrically insulated from the second semiconductor layer and the first semiconductor layer by a gate dielectric, wherein, in a vertical cross-sectional view, a source electrode has a vertical edge immediately adjacent to a first vertical edge of the first semiconductor layer and immediately adjacent to a first vertical edge of the second semiconductor layer, and wherein, in a vertical cross-sectional view, a drain electrode is spaced apart from the source electrode and has a vertical edge immediately adjacent to a second vertical edge of the first semiconductor layer and immediately adjacent to a second vertical edge of the second semiconductor layer. ### Claim 10 (depends on 9) The method of claim 9, wherein the semiconductor body further comprises a third semiconductor layer adjoining the second semiconductor layer and comprising a group III nitride, and wherein each of the first gate electrode and the second gate electrode further extends through the third semiconductor layer and is further dielectrically insulated from the third semiconductor layer by the gate dielectric. ### Claim 11 (depends on 9) The method of claim 9, wherein each of the first semiconductor layer and the second semiconductor layer comprises a doped semiconductor layer. ### Claim 12 (depends on 9) The method of claim 9, wherein each of the first semiconductor layer and the second semiconductor layer comprises an intrinsic semiconductor layer. ### Claim 13 (depends on 12) The method of claim 12, wherein the semiconductor body further comprises at least one third semiconductor layer adjoining the second semiconductor layer and comprising a doped group III nitride, and wherein each of the first gate electrode and the second gate electrode further extends through the at least one third semiconductor layer and is further dielectrically insulated from the at least one third semiconductor layer by the gate dielectric. ### Claim 14 (depends on 9) The method of claim 9, wherein a field electrode adjoins the second gate electrode. ### Claim 15 A method of forming a transistor device, the method comprising: forming a semiconductor body with a first semiconductor layer comprising a first type of group III nitride and a second semiconductor layer adjoining the first semiconductor layer and comprising a second type of group III nitride; forming a source electrode having a vertical edge immediately adjacent to a first vertical edge of the first semiconductor layer and immediately adjacent to a first vertical edge of the second semiconductor layer in a vertical cross-sectional view; forming a drain electrode spaced apart from the source electrode and having a vertical edge immediately adjacent to a second vertical edge of the first semiconductor layer and immediately adjacent to a second vertical edge of the second semiconductor layer in a vertical cross-sectional view; and forming a first gate electrode configured for generating a first conducting channel in the semiconductor body in response to a first signal driving the first gate electrode at a first slew rate and a second gate electrode configured for generating a second conducting channel in the semiconductor body in response to a second signal driving the second gate electrode at a second slew rate greater than the first slew rate, wherein the first gate electrode and the second gate electrode are spaced apart in a current flow direction of the transistor device, wherein the first gate electrode and the second gate electrode are electrically insulated with respect to each other, and wherein the first gate electrode and the second gate electrode are controlled individually with respect to each other in a mode of operation, wherein each of the first gate electrode and the second gate electrode extends through the second semiconductor layer into the first semiconductor layer and is dielectrically insulated from the second semiconductor layer and the first semiconductor layer by a gate dielectric. ### Claim 16 (depends on 15) The method of claim 15, wherein the semiconductor body further comprises a third semiconductor layer adjoining the second semiconductor layer and comprising a group III nitride, and wherein each of the first gate electrode and the second gate electrode further extends through the third semiconductor layer and is further dielectrically insulated from the third semiconductor layer by the gate dielectric. ### Claim 17 (depends on 15) The method of claim 15, wherein each of the first semiconductor layer and the second semiconductor layer comprises a doped semiconductor layer. ### Claim 18 (depends on 15) The method of claim 15, wherein each of the first semiconductor layer and the second semiconductor layer comprises an intrinsic semiconductor layer. ### Claim 19 (depends on 18) The method of claim 18, wherein the semiconductor body further comprises at least one third semiconductor layer adjoining the second semiconductor layer and comprising a doped group III nitride, and wherein each of the first gate electrode and the second gate electrode further extends through the at least one third semiconductor layer and is further dielectrically insulated from the at least one third semiconductor layer by the gate dielectric. ### Claim 20 (depends on 15) The method of claim 15, wherein a field electrode adjoins the second gate electrode.