# US 12,003,177 B2 · Method and apparatus for sensing output current in a DC-DC converter circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,003,177 B2 - Document ID: US12003177B2 - Status: Granted - Kind: B2 - Application number: 17/748,214 - Filed: 2022-05-19 - Published: 2023-11-23 - Granted: 2024-06-04 - Earliest claimed: 2022-05-19 - Assignees: STMicroelectronics S.r.l. - Applicants: STMicroelectronics S.r.l. - Inventors: Marco La Pila; Giuseppe Platania - Web page: https://patentgrep.com/patent/US12003177B2 ## CPC - H02M 3/158: including plural semiconductor devices as final control devices for a single load - H02M 1/0009: {Devices or circuits for detecting current in a converter} - H02M 3/1588: {comprising at least one synchronous rectifier element (H02M3/1582, H02M3/1584 take precedence)} - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) ## Abstract A switching regulator circuit has a high side (HS) transistor actuated during on time (TON) of a duty cycle. The output current of the switching regulator circuit is determined from sensing a transistor current flowing through the HS transistor during HS transistor on time (TON) and dividing the sensed transistor current by the duty cycle to generate an output signal indicative of the output current of the switching regulator circuit. The duty cycle is determined from a ratio of the on time (TON) and off time (TOFF) of the switching regulator circuit. ## Claims ### Claim 1 A switching regulator circuit, comprising: a high side (HS) transistor coupled between a first node and a switching node; a low side (LS) transistor coupled between the switching node and a second node; driver circuitry for controlling actuation of the HS transistor and LS transistor in accordance with a duty cycle; an inductor having a first terminal coupled to the switching node and a second terminal coupled to a third node, wherein an output current flows through the inductor; an output current detection circuit comprising: a current sensing circuit configured to sense a transistor current flowing through the HS transistor during HS transistor on time (TON); and a duty cycle detect and divide circuit configured to detect said duty cycle which controls actuation of the HS transistor and LS transistor, and divide the sensed transistor current by said duty cycle to generate an output signal indicative of the output current that flows through the inductor. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the first node is configured to receive an input voltage, the second node is configured to receive a reference voltage and the third node is an output voltage node. ### Claim 3 (depends on 1) The circuit of claim 1, wherein said duty cycle detect and divide circuit comprises: a first differential amplifier having a first input coupled to receive the sensed transistor current and a second input and an output producing said output signal; a capacitor coupled in feedback between the output of the first differential amplifier and the second input; a first switching transistor coupled between the output of the first differential amplifier and a further switching node, said first switching transistor controlled by a high side signal controlling the HS transistor; a second switching transistor coupled between the further switching node and the second node, said second switching transistor controlled by a low side signal controlling the LS transistor; and a feedback path coupled between the further switching node and the second input of the first differential amplifier. ### Claim 4 (depends on 1) The circuit of claim 1, wherein said duty cycle detect and divide circuit comprises: a first differential amplifier having a first input coupled to receive the sensed transistor current and a second input and an output producing said output signal; a capacitor coupled in feedback between the output of the first differential amplifier and the second input; and a switching feedback circuit controlled in response to alternating switching of the HS and LS transistors to alternately apply a signal at the output of the first differential amplifier and a reference voltage to the second input of the first differential amplifier. ### Claim 5 (depends on 1) The circuit of claim 1, wherein said current sensing circuit comprises: a second differential amplifier having a first input, a second input and an output; a first input transistor coupled between a first terminal of the HS transistor and the first input of the second differential amplifier; a second input transistor coupled between a second terminal of the HS transistor and the second input of the second differential amplifier; wherein said first and second input transistors are actuated during HS transistor on time (TON); an output transistor coupled between the first input of the second differential amplifier and a first intermediate node; and a resistor coupled between the first intermediate node and the second node. ### Claim 6 (depends on 5) The circuit of claim 5, wherein said current sensing circuit further comprises a low pass filter circuit coupled between the first intermediate node and the second node, said low pass filter circuit having a second intermediate node outputting the sensed transistor current. ### Claim 7 A circuit for detecting output current of a switching regulator circuit having a high side (HS) transistor actuated during on time (TON) of a duty cycle, comprising: a current sensing circuit configured to sense a transistor current flowing through the HS transistor during HS transistor on time (TON); and a duty cycle detect and divide circuit configured to detect said duty cycle, and divide the sensed transistor current by said duty cycle to generate an output signal indicative of the output current of the switching regulator circuit. ### Claim 8 (depends on 7) The circuit of claim 7, wherein the switching regulator circuit further includes a low side (LS) transistor, and wherein said duty cycle is detected as a function of a high side drive signal controlling actuation of the HS transistor and a low side drive signal controlling actuation of the LS transistor. ### Claim 9 (depends on 8) The circuit of claim 8, wherein said duty cycle detect and divide circuit comprises: a first differential amplifier having a first input coupled to receive the sensed transistor current and a second input and an output producing said output signal; a capacitor coupled in feedback between the output of the first differential amplifier and the second input; a first switching transistor coupled between the output of the first differential amplifier and a further switching node, said first switching transistor controlled by said high side drive signal; a second switching transistor coupled between the further switching node and the second node, said second switching transistor controlled by said low side drive signal; and a feedback path coupled between the further switching node and the second input of the first differential amplifier. ### Claim 10 (depends on 7) The circuit of claim 7, wherein said duty cycle detect and divide circuit comprises: a first differential amplifier having a first input coupled to receive the sensed transistor current and a second input and an output producing said output signal; a capacitor coupled in feedback between the output of the first differential amplifier and the second input; and a switching feedback circuit controlled in response to switching of the HS transistor to alternately apply a signal at the output of the first differential amplifier and a reference voltage to the second input of the first differential amplifier. ### Claim 11 (depends on 7) The circuit of claim 7, wherein said current sensing circuit comprises: a second differential amplifier having a first input, a second input and an output; a first input transistor coupled between a first terminal of the HS transistor and the first input of the second differential amplifier; a second input transistor coupled between a second terminal of the HS transistor and the second input of the second differential amplifier; wherein said first and second input transistors are actuated during HS transistor on time (TON); an output transistor coupled between the first input of the second differential amplifier and a first intermediate node; and a resistor coupled between the first intermediate node and the second node. ### Claim 12 (depends on 11) The circuit of claim 11, wherein said current sensing circuit further comprises a low pass filter circuit coupled between the first intermediate node and the second node, said low pass filter circuit having a second intermediate node outputting the sensed transistor current. ### Claim 13 A method for detecting output current of a switching regulator circuit having a high side (HS) transistor actuated during on time (TON) of a duty cycle, comprising: sensing a transistor current flowing through the HS transistor during HS transistor on time (TON); detecting said duty cycle; and dividing the sensed transistor current by said duty cycle to generate an output signal indicative of the output current of the switching regulator circuit. ### Claim 14 (depends on 13) The method of claim 13, wherein detecting said duty cycle comprises determining the duty cycle as a function of a high side drive signal controlling actuation of the HS transistor. ### Claim 15 (depends on 13) The method of claim 13, wherein the switching regulator circuit further includes a low side (LS) transistor, and wherein detecting said duty cycle comprises determining the duty cycle as a function of a high side drive signal controlling actuation of the HS transistor and a low side drive signal controlling actuation of the LS transistor. ### Claim 16 (depends on 13) The method of claim 13, wherein sensing the transistor current comprises: sampling a first voltage at a first terminal of the HS transistor during on time (TON); sampling a second voltage at a second terminal of the HS transistor during on time (TON); differentially processing the first and second voltages to generate a sensed current replicating the transistor current flowing through the HS transistor; converting the sensed current to a voltage; and smoothing the voltage to generate said sensed transistor current. ### Claim 17 (depends on 13) The method of claim 13, wherein detecting and dividing comprises: integrating a difference between the sensed transistor current and a switched signal; wherein said switched signal has a first value during the on time (TON) of the duty cycle and wherein the switched signal has a second value during an off time (TOFF) of the duty cycle. ### Claim 18 (depends on 17) The method of claim 17, wherein the first value is the output signal and the second value is a reference. ### Claim 19 (depends on 18) The method of claim 18, wherein the reference is ground.