# US 12,003,093 B2 · Electrostatic protection circuit, display substrate and display apparatus

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- Number: US 12,003,093 B2
- Document ID: US12003093B2
- Status: Granted
- Kind: B2
- Application number: 17/765,530
- Filed: 2021-06-15
- Published: 2022-10-06
- Granted: 2024-06-04
- Earliest claimed: 2020-07-29
- Assignees: Chengdu Boe Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd.
- Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd.
- Inventors: Jianchang Cai; Yue Long; Yudiao Cheng; Hongjun Zhou; Lili Du
- Web page: https://patentgrep.com/patent/US12003093B2

## CPC

- G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)}
- H02H 7/008: {for protective arrangements according to this subclass (H02H9/042, H02H9/043 take precedence; protection of spark-gaps H02H7/24)}
- H10D 89/911: {using passive elements as protective elements}
- H10D 89/931: {characterised by the dispositions of the protective arrangements}
- H10K 59/131: Interconnections, e.g. wiring lines or terminals
- G09G 2300/04: Structural and physical details of display devices
- G09G 2300/043: Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
- G09G 2330/04: Display protection
- G09G 2330/12: Test circuits or failure detection circuits included in a display system, as permanent part thereof
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10K 59/1216: {the pixel elements being capacitors}
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

Disclosed are an electrostatic protection circuit, a display substrate and a display apparatus. The electrostatic protection circuit includes: a plurality of first transistors (11) on a base substrate, each of which includes a gate, an active layer (112), a first electrode (113), a second electrode (114) and a connection part (115). Gates of the first transistors (11) are connected to each other to form a control line (12). The first electrode (113) of each first transistor (11) is electrically connected to a panel crack detect line (PL), the connection part (115) is connected between the first electrode (113) and the second electrode (114), and the active layer (112) and the gate of each first transistor (11) are arranged in an overlapping manner and insulated and separated from each other to form a first capacitor. The control line (12) is electrically connected to a first power supply line (VSS).

## Claims

### Claim 1

An electrostatic protection circuit, comprising: a plurality of first transistors on a base substrate, each of which comprises a gate, an active layer, a first electrode, a second electrode and a connection part,
wherein gates of the plurality of first transistors are connected to each other to form a control line; the first electrode of each first transistor is electrically connected to a panel crack detect line, the connection part is connected between the first electrode and the second electrode of the first transistor, and the active layer and the gate of the first transistor are arranged in an overlapping manner and insulated and separated from each other to form a first capacitor; and
the control line is electrically connected to a first power supply line, the first power supply line and the control line are in different layers insulated and separated from each other, a first via is in an insulation layer between a layer where the first power supply line is located and a layer where the control line is located, the first power supply line is electrically connected to the control line through the first via, an orthographic projection of the first capacitor near the first via on the base substrate is spaced apart from an orthographic projection of the first via on the base substrate by a first distance, and a ratio of the first distance to a size of the first capacitor in a direction perpendicular to the connection part is greater than 0.375.

### Claim 2 (depends on 1)

The electrostatic protection circuit according to claim 1, wherein the ratio of the first distance to the size of the first capacitor in the direction perpendicular to the connection part is between 0.375 and 5.

### Claim 3 (depends on 1)

The electrostatic protection circuit according to claim 1, wherein the first distance is between 15 μm and 50 μm, and the size of the first capacitor in the direction perpendicular to the connection part is between 10 μm and 40 μm.

### Claim 4 (depends on 1)

The electrostatic protection circuit according to claim 1, wherein the plurality of first transistors in the electrostatic protection circuit are arranged in two rows, at least one row of which comprises multiple first transistors, and the control line is an annular signal line.

### Claim 5 (depends on 4)

The electrostatic protection circuit according to claim 4, wherein first electrodes of the plurality of first transistors are connected to each other by a connection line, and the connection line is a semi-closed structure surrounding the control line.

### Claim 6 (depends on 5)

The electrostatic protection circuit according to claim 5, wherein both ends of the connection line are electrically connected to the panel crack detect line.

### Claim 7 (depends on 5)

The electrostatic protection circuit according to claim 5, wherein the panel crack detect line is between a layer where the gate of each first transistor is located and a layer where the first electrode of each first transistor is located, a gate insulation layer is between a layer where the panel crack detect line is located and the layer where the gate of each first transistor is located, and an interlayer dielectric layer is between the layer where the panel crack detect line is located and the layer where the first electrode of each first transistor is located.

### Claim 8 (depends on 7)

The electrostatic protection circuit according to claim 7, wherein the connection line and the panel crack detect line are electrically connected through a second via that penetrates through the interlayer dielectric layer.

### Claim 9 (depends on 7)

The electrostatic protection circuit according to claim 7, wherein the gate insulation layer and the interlayer dielectric layer both cover the panel crack detect line and the electrostatic protection circuit.

### Claim 10 (depends on 5)

The electrostatic protection circuit according to claim 5, wherein the first electrode and the second electrode of each first transistor, and the connection line are connected into an integral structure.

### Claim 11 (depends on 1)

The electrostatic protection circuit according to claim 1, wherein the connection part of the first transistor has a width between 3 μm and 10 μm.

### Claim 12 (depends on 1)

The electrostatic protection circuit according to claim 1, wherein the first power supply line is in the same layer as the first electrode and the second electrode of each first transistor.

### Claim 13 (depends on 1)

A display substrate, comprising the electrostatic protection circuit according to claim 1, wherein the display substrate has a display area and a peripheral area surrounding the display area, and the electrostatic protection circuit is in the peripheral area of the display substrate.

### Claim 14 (depends on 13)

The display substrate according to claim 13, further comprising a pixel circuit in the display area, wherein the pixel circuit comprises: a storage capacitor and a plurality of second transistors,
an active layer of each second transistor is in the same layer as the active layer of each first transistor,
a gate of each second transistor and a first electrode of the storage capacitor are in the same layer as the gate of each first transistor,
a first electrode and a second electrode of each second transistor are in the same layer as the first electrode and the second electrode of each first transistor, and
a second electrode of the storage capacitor is in the same layer as the panel crack detect line.

### Claim 15 (depends on 13)

A display apparatus, comprising the display substrate according to claim 13.