# US 12,002,913 B2 · Display backplane and fabrication method thereof, display panel and fabrication method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,913 B2 - Document ID: US12002913B2 - Status: Granted - Kind: B2 - Application number: 17/417,660 - Filed: 2020-10-22 - Published: 2022-10-27 - Granted: 2024-06-04 - Earliest claimed: 2020-10-22 - Assignees: Boe Technology Group Co., Ltd. - Applicants: BOE Technology Group Co., Ltd. - Inventors: Haixu Li; Guangcai Yuan; Zhanfeng Cao; Ke Wang; Qi Qi - Web page: https://patentgrep.com/patent/US12002913B2 ## CPC - H10H 20/857: Interconnections, e.g. lead-frames, bond wires or solder balls - H10W 90/00: Package configurations - H10H 20/01: Manufacture or treatment - H10H 20/0364: {of interconnections} - H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The present disclosure provides a display backplane including an array substrate including at least one pixel unit each including at least one TFT; a planarization layer covering the array substrate; a pad layer including pads on the planarization layer, surface of the pad away from the planarization layer being first surface, each pixel unit being provided with one pad electrically coupled to a driving thin film transistor in a corresponding pixel unit through via hole penetrating through the planarization layer; a passivation layer covering the pad layer and including through holes, each pad corresponding to one through hole, such that the first surface of each pad is exposed through corresponding through hole, and area of top opening of through hole is smaller than area of bottom opening thereof. The present disclosure further provides a fabrication method of the display backplane, a display panel and a fabrication method thereof. ## Claims ### Claim 1 A display backplane, characterized in that the display backplane comprises: an array substrate comprising at least one pixel unit, each pixel unit comprising at least one thin film transistor; a planarization layer covering the array substrate; a pad layer comprising a plurality of pads on the planarization layer, a surface of the pad away from the planarization layer being a first surface, each pixel unit being provided with one of the plurality of pads, and the pad being electrically coupled to a driving thin film transistor in the pixel unit through a via hole which penetrates through the planarization layer; and a passivation layer covering the pad layer and comprising a plurality of through holes, each of the plurality of pads corresponding to one through hole, such that the first surface of each of the plurality of pads is exposed through a corresponding through hole, and an area of a top opening of the through hole is smaller than an area of a bottom opening of the through hole. ### Claim 2 (depends on 1) The display backplane of claim 1, characterized in that an angle between a sidewall of the through hole and the first surface of the pad layer is between 10° and 80°. ### Claim 3 (depends on 1) The display backplane of claim 1, characterized in that a material of the passivation layer is silicon nitride, and a thickness of the passivation layer is between 3000 angstroms and 4000 angstroms. ### Claim 4 (depends on 1) A display panel, characterized in that the display panel comprises: a display backplane, the display backplane being the display backplane of claim 1; a light emitting diode (LED) layer comprising at least one LED unit, wherein each LED unit comprises a plurality of LED pins, each of the plurality of LED pins corresponds to one of the plurality of pads, and a portion of each of the plurality of LED pins is arranged in a corresponding through hole and is electrically coupled to the pad. ### Claim 5 (depends on 4) The display panel of claim 4, characterized in that the LED pin comprises a pin body and a flange around the pin body, the flange being disposed in the corresponding through hole. ### Claim 6 (depends on 5) The display panel of claim 5, characterized in that the flange is disposed at an end of the pin body facing the pad, and a bottom surface of the flange and a bottom surface of the pin body are both soldered to a corresponding pad. ### Claim 7 (depends on 5) The display panel of claim 5, characterized in that a width of the flange is between 0.1 μm and 0.2 μm. ### Claim 8 (depends on 4) The display panel of claim 4, characterized in that the LED pin comprises a pin core and a pin skin cladding the pin core, and a material of the pin skin is a material capable of eutectic soldering. ### Claim 9 (depends on 8) The display panel of claim 8, characterized in that a material of the pin core is copper, and the material of the pin skin is selected from at least one of the following alloys: copper-nickel alloy, copper-tin alloy, and silver-tin alloy. ### Claim 10 (depends on 8) The display panel of claim 8, characterized in that a thickness of the pin skin is no more than one tenth of a diameter of the pin core. ### Claim 11 (depends on 10) The display panel of claim 10, characterized in that the pin core has a diameter between 5000 angstroms and 7000 angstroms. ### Claim 12 (depends on 4) The display panel of claim 4, characterized in that the LED is a micro-LED or a mini-LED. ### Claim 13 A fabrication method of a display backplane, characterized in that the fabrication method comprises: providing an array substrate, the array substrate comprising at least one pixel unit, each pixel unit comprising at least one thin film transistor, and the at least one thin film transistor comprising a driving thin film transistor; forming a planarization layer covering the array substrate, the planarization layer being formed with a plurality of via holes, each of the plurality of via holes corresponding to the driving thin film transistor in one pixel unit; forming a pad layer comprising a plurality of pads on the planarization layer, a surface of the pad away from the planarization layer being a first surface, each pixel unit being provided with one of the plurality of pads, and the pad being electrically coupled to the driving thin film transistor in the pixel unit through the via hole which penetrates through the planarization layer; and forming a passivation layer covering the pad layer and comprising a plurality of through holes, each pad corresponding to one through hole, such that the first surface of the pad is exposed through a corresponding through hole, and an area of a top opening of the through hole is smaller than an area of a bottom opening of the through hole. ### Claim 14 A fabrication method of a display panel, characterized in that the fabrication method of the display panel comprises: providing an array substrate, the array substrate comprising at least one pixel unit, each pixel unit comprising at least one thin film transistor, and the at least one thin film transistor comprising a driving thin film transistor; forming a planarization layer covering the array substrate and formed with a plurality of via holes, each of the plurality of via holes corresponding to the driving thin film transistor in one pixel unit; forming a pad layer comprising a plurality of pads on the planarization layer, a surface of the pad away from the planarization layer being a first surface, each pixel unit being provided with one of the plurality of pads, and the pad being electrically coupled to the driving thin film transistor in the pixel unit through the via hole which penetrates through the planarization layer; forming a passivation layer to obtain a display backplane, the passivation layer covering the pad layer and comprising a plurality of through holes, each pad corresponding to one through hole, such that the first surface of the pad is exposed through a corresponding through hole, and an area of a top opening of the through hole is smaller than an area of a bottom opening of the through hole; and transferring a light emitting diode (LED) layer onto the display backplane such that each LED pin of the LED layer falls into a corresponding through hole and contacts with a corresponding pad; and soldering each LED of the LED layer with a corresponding pad through a corresponding LED pin.