# US 12,002,891 B2 · Diode and method of making the same

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- Number: US 12,002,891 B2
- Document ID: US12002891B2
- Status: Granted
- Kind: B2
- Application number: 17/855,735
- Filed: 2022-06-30
- Published: 2023-09-21
- Granted: 2024-06-04
- Earliest claimed: 2021-06-30
- Assignees: The Curators of the University of Missouri
- Applicants: Alex Usenko; Anthony Caruso; Steven Bellinger
- Inventors: Alex Usenko; Anthony Caruso; Steven Bellinger
- Web page: https://patentgrep.com/patent/US12002891B2

## CPC

- H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00)
- H10D 8/01: Manufacture or treatment
- H10D 8/041: {of multilayer diodes}
- H10D 8/045: {of PN junction diodes}
- H10D 8/50: PIN diodes
- H10D 62/60: Impurity distributions or concentrations
- H10P 10/128: {by direct semiconductor to semiconductor bonding}
- H10P 32/1404: {using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase}
- H10P 32/171: {being group IV material}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of producing a four-layer silicon diode, including selecting a first silicon wafer, wherein said first silicon wafer is CZ-grown B-doped with <100> orientation, a resistivity of less than 0.01 Ohm-cm, and an oxygen content of greater than 10 ppma, and then selecting a second silicon wafer, wherein said second silicon wafer is CZ-grown P-doped with <100> orientation, a resistivity of less than 0.005 Ohm-cm, and an oxygen content of greater than 10 ppma, followed by cleaning the respective first and second silicon wafers. The wafers are then HF treated to yield respective first and second cleaned wafers, the first cleaned wafer is positioned into a first furnace and the second cleaned wafer is positioned into a second furnace, wherein the first and second furnaces are not unitary. Next is annealing the respective first and second cleaned wafers in a reducing atmosphere to yield respective first and second respective out-diffused gradient wafers, followed by bonding together respective first and second heat-treated wafers to yield a mated and/or bonded four-layer substrate having a first heavy doped n-type layer, a second gradient doped n-type layer, a third gradient doped p-type layer, and a fourth heavy doped p-type layer.

## Claims

### Claim 1

A method of producing a four-layer silicon diode; comprising:
a) selecting a first CZ-grown silicon wafer, wherein said first CZ-grown silicon wafer is B-doped with <100> orientation, a resistivity of less than 0.01 Ohm-cm, and an oxygen content of greater than 10 ppma;
b) selecting a second CZ-grown silicon wafer, wherein said second CZ-grown silicon wafer is P-doped with <100> orientation, a resistivity of less than 0.005 Ohm-cm, and an oxygen content of greater than 10 ppma;
c) heating respective CZ-grown silicon wafers in a reducing atmosphere to yield respective out-diffused CZ-grown wafers;
d) preparing surfaces of the respective out-diffused CZ-grown wafers for furnace annealing;
e) HF treating respective out-diffused CZ-grown wafers;
f) positioning the first out-diffused CZ-grown wafer into a first furnace;
g) positioning the second out-diffused CZ-grown wafer into a second furnace, wherein the first and second furnaces are not unitary;
h) annealing the respective first and second out-diffused CZ-grown wafers in a reducing atmosphere to yield respective first and second respective out-diffused gradient wafers;
i) plasma treating respective first and second vacuum-treated out-diffused gradient wafers to grow a thin silica layer thereupon so as to yield respective first and second plasma treated wafers;
j) vacuum treating respective first and second out-diffused gradient wafers to yield respective first and second vacuum-treated out-diffused gradient wafers;
k) mating respective first and second plasma treated wafers to yield a four-layered diode structure.

### Claim 2 (depends on 1)

The method of producing a four-layer silicon diode of claim 1 wherein the first out-diffused gradient wafer further defines a first heavy doped n-type layer and a second gradient doped n-type; and wherein the second first heavy doped p-type layer further defines a third gradient doped p-type layer and a fourth heavy doped p-type layer.

### Claim 3 (depends on 1)

The method of producing a four-layer silicon diode of claim 1 wherein the respective first and second prepared wafers are annealed between 1000 degrees Celsius and 1350 degrees Celsius for between 1 and 200 hours.

### Claim 4 (depends on 1)

The method of producing a four-layer silicon diode of claim 1 wherein the respective said first and second prepared wafers are annealed in respective rapid thermal processing chambers for between 1 and 60 seconds.

### Claim 5 (depends on 4)

The method of producing a four-layer silicon diode of claim 4 wherein, after annealing, the respective first and second respective out-diffused gradient wafers were cooled at a rate of between 40 degrees Celsius per second and 400 degrees Celsius per second.

### Claim 6 (depends on 1)

The method of producing a four-layer silicon diode of claim 1 and further comprising the step of before j, bonding respective first and second plasma treated wafers to yield a four-layered diode structure.

### Claim 7 (depends on 1)

The method of producing a four-layer silicon diode of claim 1 and further comprising the step of after i) and before j), surface-treating the respective first and second first and second plasma treated wafers with argon ion bombardment.

### Claim 8 (depends on 1)

The method of producing a four-layer silicon diode of claim 1 wherein during heating, furnace temperature is ramped to 600 degrees Celsius at a rate lower than 10 degrees Celsius per minute.

### Claim 9 (depends on 1)

The method of producing a four-layer silicon diode of claim 1 and further comprising the step of after i) and before j), surface-treating the respective first and second first and second plasma treated wafers with antimony ion implantation; and wherein antimony ion implantation amorphizes ion implanted surfaces.

### Claim 10 (depends on 1)

The method of producing a four-layer silicon diode of claim 1 wherein before step j), respective first and second first and second plasma treated wafers are bathed in hydrofluoric acid.

### Claim 11 (depends on 1)

The method of producing a four-layer silicon diode of claim 1 wherein step j) occurs immediately after respective first and second first and second plasma treated wafers wafers are bathed in hydrofluoric acid.