# US 12,002,890 B2 · Semiconductor protection device

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- Number: US 12,002,890 B2
- Document ID: US12002890B2
- Status: Granted
- Kind: B2
- Application number: 17/585,284
- Filed: 2022-01-26
- Published: 2022-11-24
- Granted: 2024-06-04
- Earliest claimed: 2021-05-21
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jaehyun Yoo; Kyuok Lee; Uihui Kwon; Junhyeok Kim; Yongwoo Jeon; Dawon Jeong; Jaehyok Ko
- Web page: https://patentgrep.com/patent/US12002890B2

## CPC

- H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00)
- H10D 62/114: {PN junction isolations}
- H10D 8/021: {of breakdown diodes}
- H10D 62/051: {Forming charge compensation regions, e.g. superjunctions}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 64/112: {comprising multiple field plate segments}
- H10D 89/711: {using bipolar transistors as protective elements}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 64/111: {Field plates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor protection device includes: an N-type epitaxial layer, a device isolation layer disposed in the N-type epitaxial layer, an N-type drift region disposed below the device isolation layer, an N-type well disposed in the N-type drift region, first and second P-type drift regions, respectively disposed to be in contact with the device isolation layer, and spaced apart from the N-type drift region, first and second P-type doped regions, respectively disposed in the first and second P-type drift regions, first and second N-type floating wells, respectively disposed in the first and second P-type drift regions to be spaced apart from the first and second P-type doped regions, and disposed to be in contact with the device isolation layer, and first and second contact layer, respectively disposed to cover the first and second N-type floating well, to be in contact with the device isolation layer.

## Claims

### Claim 1

A semiconductor protection device comprising:
an N-type buried layer on a P-type substrate;
an N-type epitaxial layer on the N-type buried layer;
a device isolation layer on an upper surface of the N-type epitaxial layer;
an N-type drift region below the device isolation layer;
an N-type well in the N-type drift region;
first and second P-type drift regions, each of the first and second P-type drift regions in contact with a respective opposite end of the device isolation layer and spaced apart from the N-type drift region;
first and second high voltage P-type wells below the first and second P-type drift regions and in contact with the N-type buried layer;
first and second P-type wells, each of the first and second P-type wells in a respective one of the first and second P-type drift regions;
first and second N-type floating wells, each of the first and second N-type floating wells in the respective one of the first and second P-type drift regions and spaced apart from a respective one of the first and second P-type wells, and wherein each of the first and second N-type floating wells is in contact with the respective one of the opposite ends of the device isolation layer;
first and second P-type doped regions, each of the first and second P-type doped regions in the respective one of the first and second P-type wells;
a first contact layer on the N-type epitaxial layer and in contact with the first N-type floating well and the device isolation layer;
a second contact layer on the N-type epitaxial layer and in contact with the second N-type floating well and the device isolation layer;
a cathode electrode on the first P-type doped region and spaced apart from the first contact layer; and
an anode electrode on the second P-type doped region and spaced apart from the second contact layer.

### Claim 2 (depends on 1)

The semiconductor protection device of claim 1, wherein each of the first and second N-type floating wells is below the device isolation layer.

### Claim 3 (depends on 1)

The semiconductor protection device of claim 1, wherein a lower surface of the N-type well and lower surfaces of the first and second N-type floating wells have a same width.

### Claim 4 (depends on 1)

The semiconductor protection device of claim 1, wherein the N-type well and the first and second N-type floating wells are doped with the same N-type impurities.

### Claim 5 (depends on 1)

The semiconductor protection device of claim 1, wherein the first and second N-type floating wells are doped at the same impurity concentration.

### Claim 6 (depends on 1)

The semiconductor protection device of claim 1, further comprising:
an N-type doped region in the device isolation layer, wherein the N-type doped region is in contact with an upper surface of the N-type epitaxial layer and the N-type well, and
wherein a thickness of the N-type doped region is less than a thickness of the device isolation layer.

### Claim 7 (depends on 1)

The semiconductor protection device of claim 1, wherein the first and second contact layers comprise a material including at least one of polysilicon, tungsten, and aluminum.

### Claim 8 (depends on 1)

The semiconductor protection device of claim 1, wherein the first and second P-type doped regions do not overlap the first and second contact layers.

### Claim 9

A semiconductor protection device comprising:
an N-type epitaxial layer;
a device isolation layer on an upper surface of the N-type epitaxial layer;
an N-type drift region below the device isolation layer;
an N-type well in the N-type drift region;
first and second P-type drift regions, each of the first and second P-type drift regions in contact with a respective opposite end of the device isolation layer, and spaced apart from the N-type drift region;
first and second P-type doped regions, each of the first and second P-type doped regions in a respective one of the first and second P-type drift regions;
first and second N-type floating wells, each of the first and second N-type floating wells in the respective one of the first and second P-type drift regions and spaced apart from a respective one of the first and second P-type doped regions, and wherein each of the first and second N-type floating wells is in contact with the respective one of the opposite ends of the device isolation layer;
a first contact layer on the N-type epitaxial layer and in contact with the first N-type floating well and the device isolation layer; and
a second contact layer on the N-type epitaxial layer and in contact with the second N-type floating well and the device isolation layer.

### Claim 10 (depends on 9)

The semiconductor protection device of claim 9, further comprising:
first and second P-type wells, each of the first and second P-type wells in the respective one of the first and second P-type drift regions, and wherein the first and second P-type wells each overlap the respective one of the first and second P-type doped regions.

### Claim 11 (depends on 10)

The semiconductor protection device of claim 10, wherein the first P-type doped region is in the first P-type well, and wherein the second P-type doped region is in the second P-type well.

### Claim 12 (depends on 9)

The semiconductor protection device of claim 9, wherein the first and second N-type floating wells are mirror-symmetrical with respect to the N-type well.

### Claim 13 (depends on 9)

The semiconductor protection device of claim 9, wherein the first and second N-type floating wells are in contact with the device isolation layer.

### Claim 14 (depends on 9)

The semiconductor protection device of claim 9, wherein the first and second N-type floating wells are doped at a similar impurity concentration as the N-type well.

### Claim 15

A semiconductor protection device comprising:
a first conductivity-type epitaxial layer comprising first and second regions, wherein the first region comprises:
a device isolation layer on an upper surface of the first conductivity-type epitaxial layer, wherein the device isolation layer overlaps a central axis of the semiconductor protection device;
a first conductivity-type drift region below the device isolation layer;
a first conductivity-type well in the first conductivity-type drift region;
a second conductivity-type drift region in contact with the device isolation layer and spaced apart from the first conductivity-type drift region;
a high voltage second conductivity-type well below the second conductivity-type drift region;
a second conductivity-type doped region in the second conductivity-type drift region;
a first conductivity-type floating well spaced apart from the second conductivity-type doped region in the second conductivity-type drift region;
a contact layer on the first conductivity-type epitaxial layer, wherein the contact layer overlaps the first conductivity-type floating well and is in contact with the device isolation layer; and
an electrode on the second conductivity-type doped region and spaced apart from the contact layer, and
wherein the second region and the first region are mirror-symmetrical.

### Claim 16 (depends on 15)

The semiconductor protection device of claim 15, further comprising:
a first conductivity-type doped region in contact with the first conductivity-type well at the central axis.

### Claim 17 (depends on 15)

The semiconductor protection device of claim 15, wherein the first conductivity-type floating well is spaced apart from the device isolation layer.

### Claim 18 (depends on 15)

The semiconductor protection device of claim 15, wherein the first conductivity-type floating well is in contact with the device isolation layer.

### Claim 19 (depends on 15)

The semiconductor protection device of claim 15, wherein the first conductivity-type floating well does not overlap the contact layer.

### Claim 20 (depends on 15)

The semiconductor protection device of claim 15, wherein the first conductivity-type floating well is below the device isolation layer.