# US 12,002,885 B2 · Gate contact and via structures in semiconductor devices

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- Number: US 12,002,885 B2
- Document ID: US12002885B2
- Status: Granted
- Kind: B2
- Application number: 17/470,548
- Filed: 2021-09-09
- Published: 2022-08-11
- Granted: 2024-06-04
- Earliest claimed: 2021-02-11
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chung-Liang Cheng; Sheng-Tsung Wang; Huang-Lin Chao
- Web page: https://patentgrep.com/patent/US12002885B2

## CPC

- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10W 20/054: {by selectively removing parts thereof (H10W20/034 takes precedence)}
- H10W 20/0698: {Local interconnections}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10P 14/432: {using selective deposition}
- H10W 20/047: {by introducing additional elements therein}
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W 20/076: {in via holes or trenches}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the fin structure adjacent to the S/D region. The gate structure includes a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack. The gate capping structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed within the gate capping structure and a first via structure disposed on the first contact structure.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a fin structure disposed on the substrate;
a source/drain (S/D) region disposed on the fin structure;
a gate structure disposed on the fin structure adjacent to the S/D region,
wherein the gate structure comprises a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack,
wherein the gate capping structure comprises a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap;
a first contact structure disposed within the gate capping structure, wherein a top surface of the first contact structure is substantially coplanar with a top surface of the insulating gate cap; and
a first via structure disposed on the first contact structure.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first contact structure is separated from the gate stack by a portion of the conductive gate cap.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein a first portion of the first contact structure is disposed within the conductive gate cap and a second portion of the first contact structure is disposed within the insulating gate cap.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising an etch stop layer disposed on the gate capping structure, wherein a portion of the first via structure is disposed within the etch stop layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising an interlayer dielectric (ILD) layer disposed over the gate capping structure, wherein a portion of the first via structure is disposed within the ILD layer.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising:
an etch stop layer disposed on the gate capping structure; and
an interlayer dielectric (ILD) layer disposed on the etch stop layer,
wherein a first portion of the first via structure is disposed within the etch stop layer and a second portion of the first via structure is disposed within the ILD layer, and
wherein the second portion is thicker than the first portion.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the first contact structure and the first via structure comprise materials different from each other.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein a ratio of a thickness of the first contact structure to a thickness of the first via structure ranges from about 1:2 to about 1:6.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein a ratio of a thickness of the conductive gate cap to a thickness of the insulating gate cap ranges from about 1:1 to about 1:2.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, further comprising a second contact structure on the S/D region.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, further comprising a second via structure on the second contact structure, wherein materials of the first and second via structures are same as each other.

### Claim 12

A semiconductor device, comprising:
a substrate;
a fin structure disposed on the substrate;
first and second source/drain (S/D) regions disposed on the fin structure;
first and second S/D contact structures disposed on the first and second S/D regions, respectively;
a S/D via structure disposed on the first S/D contact structure;
first and second gate structures disposed on the fin structure, wherein each of the first and second gate structures comprises a gate stack and a gate capping structure;
a gate contact structure disposed within the gate capping structure of the first gate structure; and
a merged via-contact structure disposed on the second S/D contact structure and within the gate capping structure of the second gate structure, wherein a first portion of the merged via-contact structure is disposed in a conductive gate cap of the gate capping structure of the second gate structure.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein a second portion of the merged via-contact structure is disposed with the in an insulating gate cap of the gate capping structure of the second gate structure.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, further comprising a gate via structure disposed on the gate contact structure.

### Claim 15

A semiconductor device, comprising:
a substrate;
a source/drain (S/D) region disposed on the substrate;
a gate stack disposed on the substrate;
a capping structure disposed on the gate stack; and
a contact structure disposed in the capping structure, wherein the contact structure is separated from the gate stack by a portion of the capping structure, and wherein a top surface of the contact structure is substantially coplanar with a top surface of the capping structure.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the capping structure comprises:
a conductive gate cap disposed on the gate stack; and
an insulating gate cap disposed on the conductive gate cap.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the capping structure comprises a conductive gate cap and an insulation cap; and
wherein a first portion of the contact structure is disposed in the conductive gate cap and a second portion of the contact structure is disposed in the insulating cap.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein the capping structure comprises a T-shaped cross-sectional profile.

### Claim 19 (depends on 12)

The semiconductor device of claim 12, wherein the gate contact structure and the merged via contact comprise materials different from each other.

### Claim 20 (depends on 12)

The semiconductor device of claim 12, wherein sidewalls of the merged via contact is in contact with the second S/D contact structure.