# US 12,002,878 B2 · Implanted isolation for device integration on a common substrate

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- Number: US 12,002,878 B2
- Document ID: US12002878B2
- Status: Granted
- Kind: B2
- Application number: 18/085,677
- Filed: 2022-12-21
- Published: 2023-04-20
- Granted: 2024-06-04
- Earliest claimed: 2020-12-02
- Assignees: GlobalFoundries U.S. Inc.
- Applicants: GlobalFoundries U.S. Inc.
- Inventors: Siva P. Adusumilli; Mark Levy; Jeonghyun Hwang
- Web page: https://patentgrep.com/patent/US12002878B2

## CPC

- H10D 30/4732: {using Group III-V semiconductor material}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 62/40: Crystalline structures
- H10D 62/8303: {Diamond}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 84/82: of only field-effect components
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 10/40: Vertical BJTs {(Vertical Heterojunction BJTs H10D10/821)}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Structures including devices, such as transistors, integrated on a semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a semiconductor substrate. A first transistor is formed in a first device region of a semiconductor substrate, and a second transistor is formed in a second device region of the semiconductor substrate. The second transistor includes a layer stack on the semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material. A polycrystalline layer includes a section that is positioned in the semiconductor substrate beneath the first device region.

## Claims

### Claim 1

A method comprising:
forming a first section of a polycrystalline layer in a semiconductor substrate beneath a first device region of the semiconductor substrate;
forming a first transistor in the first device region;
forming a layer stack including a layer comprising a III-V compound semiconductor material in a second device region of the semiconductor substrate; and
forming a second transistor using the layer stack.

### Claim 2 (depends on 1)

The method of claim 1 further comprising:
forming an isolation region in the layer stack.

### Claim 3 (depends on 2)

The method of claim 2 wherein the isolation region and the polycrystalline layer are concurrently formed.

### Claim 4 (depends on 2)

The method of claim 2 wherein the semiconductor substrate includes a top surface, the first section of the polycrystalline layer is located at a first depth relative to the top surface of the semiconductor substrate, the layer stack includes a top surface, the isolation region is located at a second depth relative to the top surface of the layer stack, and the second depth is less than the first depth.

### Claim 5 (depends on 1)

The method of claim 1 further comprising:
patterning a trench in the semiconductor substrate,
wherein the layer stack is formed on the semiconductor substrate inside the trench.

### Claim 6 (depends on 5)

The method of claim 5 further comprising:
forming a polycrystalline region in the semiconductor substrate adjacent to the trench.

### Claim 7 (depends on 6)

The method of claim 6 wherein the semiconductor substrate includes a first surface, and the polycrystalline region extends from the first surface to the first section of the polycrystalline layer.

### Claim 8 (depends on 7)

The method of claim 7 wherein the semiconductor substrate has a second surface at a bottom of the trench, the trench includes a sidewall that extends from the first surface to the second surface, the layer stack is positioned on the second surface of the semiconductor substrate, and the polycrystalline region is positioned adjacent to the sidewall of the trench.

### Claim 9 (depends on 8)

The method of claim 8 further comprising:
forming a shallow trench isolation region in the semiconductor substrate,
wherein the shallow trench isolation region is laterally positioned between the first device region and the second device region, and the polycrystalline region is laterally positioned between the sidewall of the trench and the shallow trench isolation region.

### Claim 10 (depends on 8)

The method of claim 8 further comprising:
forming a second section of the polycrystalline layer in the semiconductor substrate beneath the second surface of the semiconductor substrate at the bottom of the trench.

### Claim 11 (depends on 8)

The method of claim 8 wherein the polycrystalline layer is absent beneath the second surface of the semiconductor substrate at the bottom of the trench.

### Claim 12 (depends on 6)

The method of claim 6 further comprising:
forming a shallow trench isolation region in the semiconductor substrate,
wherein the shallow trench isolation region is laterally positioned between the first device region and the second device region, and the first section of the polycrystalline layer extends laterally beneath the shallow trench isolation region to the polycrystalline region.

### Claim 13 (depends on 1)

The method of claim 1 wherein the semiconductor substrate includes a buried oxide layer in the first device region, and the buried oxide layer is positioned between the first section of the polycrystalline layer and the first device region.

### Claim 14 (depends on 1)

The method of claim 1 wherein the semiconductor substrate has a top surface, and the first section of the polycrystalline layer extends laterally relative to the top surface beneath an entirety of the first device region.

### Claim 15 (depends on 14)

The method of claim 14 wherein the semiconductor substrate has a third device region, and further comprising:
forming a third transistor in the third device region; and
forming a second section of the polycrystalline layer that is positioned in the semiconductor substrate beneath the second device region.

### Claim 16 (depends on 15)

The method of claim 15 wherein the second section of the polycrystalline layer extends laterally relative to the top surface beneath an entirety of the third device region.

### Claim 17 (depends on 15)

The method of claim 15 wherein the first transistor and the second transistor are different types of transistors.

### Claim 18 (depends on 17)

The method of claim 17 wherein the first transistor is a field-effect transistor including a source/drain region positioned in the semiconductor substrate at least in part beneath the top surface, and the third transistor is a bipolar junction transistor including a terminal positioned in the semiconductor substrate at least in part beneath the top surface.

### Claim 19 (depends on 1)

The method of claim 1 wherein the semiconductor substrate comprises a single-crystal semiconductor material having a diamond crystal lattice structure and a <111> crystal orientation.

### Claim 20 (depends on 19)

The method of claim 19 wherein the semiconductor substrate is a bulk substrate, the single-crystal semiconductor material comprises single-crystal silicon, and the III-V compound semiconductor material comprises gallium nitride that is substantially single crystal.