# US 12,002,874 B2 · Buried power rail contact

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,002,874 B2
- Document ID: US12002874B2
- Status: Granted
- Kind: B2
- Application number: 17/384,908
- Filed: 2021-07-26
- Published: 2023-01-26
- Granted: 2024-06-04
- Earliest claimed: 2021-07-26
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Junli Wang; Ruilong Xie; Brent Anderson; Chen Zhang; Heng Wu
- Web page: https://patentgrep.com/patent/US12002874B2

## CPC

- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D 84/837: {comprising vertical IGFETs}
- H10W 20/021: {of interconnections within wafers or substrates}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0696: {by using sacrificial placeholders, e.g. using sacrificial plugs}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/427: {Power or ground buses}
- H10D 30/6728: {Vertical TFTs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a power rail contact at least partially disposed between a first source/drain region of a first vertical fin structure and a second source/drain region of a second vertical fin structure. The power rail contact is in contact with a buried power rail disposed under the first and second vertical fin structures. The power rail contact is in contact with at least one of the first and second source/drain regions. A contact cap is disposed above the power rail contact.

## Claims

### Claim 1

A semiconductor structure comprising:
a power rail contact at least partially disposed between opposing sidewalls of a first source/drain region of a first vertical fin structure and a second source/drain region of a second vertical fin structure, wherein a top surface of the power rail contact is below a top surface of the first source/drain region and the second source/drain region, and a bottom surface of the power rail contact is below a bottom surface of the first source/drain region and the second source/drain region;
a buried power rail disposed under the first and second vertical fin structures, and on the bottom surface of the power rail contact; and
a contact cap disposed above the power rail contact;
wherein the first vertical fin structure comprises a metal-based gate layer disposed above the first source/drain region and in contact with a top surface of the contact cap; and
wherein the first vertical fin structure and the second vertical fin structure together form a single vertical field-effect transistor and comprise the metal-based gate layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1 further comprising an insulative layer disposed around at least a portion of each of the first and second source/drain regions, an upper surface of the contact cap being non-coplanar with an upper surface of the insulative layer.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2 wherein the upper surface of the contact cap is higher than the upper surface of the insulative layer in a fin direction, the fin direction being a direction in which the first and second vertical fin structures extend.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3 wherein at least a portion of the contact cap is higher than the first and second source/drain regions in the fin direction.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1 wherein:
the first vertical fin structure comprises a fin extending from the first source/drain region and an insulative layer disposed between the fin and the metal-based gate layer; and
the insulative layer does not overlay the contact cap.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1 wherein the power rail contact is formed of a silicide material.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the metal-based gate layer is further disposed on sidewalls of the first vertical fin structure and the second vertical fin structure.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, further comprising a third source/drain region disposed over the first vertical fin structure and a fourth source/drain region disposed over the second vertical fin structure.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, further comprising a source/drain contact disposed over the third source/drain region and the fourth source/drain region.

### Claim 10

A semiconductor device comprising:
a first vertical fin structure comprising a first source/drain region;
a second vertical fin structure comprising a second source/drain region;
a buried power rail disposed under the first and second vertical fin structures and below the first and second source/drain regions;
a power rail contact at least partially disposed between opposing sidewalls of the first and second source/drain regions and in contact with the buried power rail, the power rail contact being in contact with at least one of the first and second source/drain regions, wherein a top surface of the power rail contact is below a top surface of the first source/drain region and the second source/drain region, and a bottom surface of the power rail contact is below a bottom surface of the first and second source/drain regions; and
a contact cap disposed above the power rail contact;
wherein the first vertical fin structure comprises a metal-based gate layer disposed above the first source/drain region and in contact with a top surface of the contact cap; and
wherein the first vertical fin structure and the second vertical fin structure together form a single vertical field-effect transistor and comprise the metal-based gate layer.

### Claim 11 (depends on 10)

The semiconductor device of claim 10 wherein the semiconductor device comprises an insulative layer disposed around at least a portion of each of the first and second source/drain regions, an upper surface of the contact cap being non-coplanar with an upper surface of the insulative layer.

### Claim 12 (depends on 11)

The semiconductor device of claim 11 wherein the upper surface of the contact cap is higher than the upper surface of the insulative layer in a fin direction, the fin direction being a direction in which the first and second vertical fin structures extend.

### Claim 13 (depends on 12)

The semiconductor device of claim 12 wherein at least a portion of the contact cap is higher than the first and second source/drain regions in the fin direction.

### Claim 14 (depends on 10)

The semiconductor device of claim 10 wherein:
the first vertical fin structure comprises a fin extending from the first source/drain region and an insulative layer disposed between the fin and the metal-based gate layer; and
the insulative layer does not overlay the contact cap.

### Claim 15 (depends on 10)

The semiconductor device of claim 10 wherein the power rail contact is formed of a silicide material.

### Claim 16 (depends on 10)

The semiconductor device of claim 10, wherein the metal-based gate layer is further disposed on sidewalls of the first vertical fin structure and the second vertical fin structure.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, further comprising a third source/drain region disposed over the first vertical fin structure and a fourth source/drain region disposed over the second vertical fin structure.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, further comprising a source/drain contact disposed over the third source/drain region and the fourth source/drain region.

### Claim 19

An integrated circuit, comprising:
one or more semiconductor structures, wherein at least one of the one or more semiconductor structures comprises:
a power rail contact at least partially disposed between opposing sidewalls of a first source/drain region of a first vertical fin structure and a second source/drain region of a second vertical fin structure, wherein a top surface of the power rail contact is below a top surface of the first source/drain region and the second source/drain region, and a bottom surface of the power rail contact is below a bottom surface of the first source/drain region and the second source/drain region;
a buried power rail disposed under the first and second vertical fin structures, and on the bottom surface of the power rail contact; and
a contact cap disposed above the power rail contact;
wherein the first vertical fin structure comprises a metal-based gate layer disposed above the first source/drain region and in contact with a top surface of the contact cap; and
wherein the first vertical fin structure and the second vertical fin structure together form a single vertical field-effect transistor and comprise the metal-based gate layer.

### Claim 20 (depends on 19)

The integrated circuit of claim 19 wherein the at least one of the one or more semiconductor structures comprises an insulative layer disposed around at least a portion of each of the first and second source/drain regions, an upper surface of the contact cap being non-coplanar with an upper surface of the insulative layer.