# US 12,002,872 B2 · Structure and formation method of semiconductor device structure

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,002,872 B2
- Document ID: US12002872B2
- Status: Granted
- Kind: B2
- Application number: 17/872,562
- Filed: 2022-07-25
- Published: 2022-11-10
- Granted: 2024-06-04
- Earliest claimed: 2015-05-22
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Po-Chi Wu; Chai-Wei Chang; Kuo-Hui Chang; Yi-Cheng Chao
- Web page: https://patentgrep.com/patent/US12002872B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.

## Claims

### Claim 1

A semiconductor device, comprising:
a gate stack over a semiconductor substrate, the gate stack comprising a gate dielectric layer, a work function layer, and a conductive fill layer, the work function layer extending along sidewalls and a bottommost surface of the conductive fill layer, wherein a topmost surface of the conductive fill layer is above a topmost surface of the gate dielectric layer in a cross-sectional view;
a dielectric cap element over the gate stack, the dielectric cap element being in physical contact with the topmost surface of the conductive fill layer, a portion of the conductive fill layer protruding above a bottommost surface of the dielectric cap element in the cross-sectional view;
a spacer element extending along a sidewall of the dielectric cap element and a sidewall of the gate stack, the spacer element having an inner sidewall closest to the sidewall of the gate stack, wherein a first portion of the gate dielectric layer is interposed between the work function layer and the semiconductor substrate, wherein a second portion of the gate dielectric layer is interposed between the work function layer and the spacer element; and
a source/drain region extending into the semiconductor substrate, a top surface of the source/drain region being above a bottom surface of the spacer element.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the topmost surface of the conductive fill layer is above a topmost surface of the work function layer in the cross-sectional view.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein a first distance between outermost opposite sidewalls of the dielectric cap element at a point adjacent an interface between the dielectric cap element and the conductive fill layer is less than a second distance between outermost opposite sidewalls of the dielectric cap element at an upper surface of the dielectric cap element in the cross-sectional view.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a lower portion of the inner sidewall of the spacer element has a steeper slope than an upper portion of the inner sidewall of the spacer element.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein an interface between the lower portion and the upper portion is above an upper surface of the conductive fill layer.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, wherein a slope of the lower portion of the inner sidewall of the spacer element is in a range from 85 degrees to 95 degrees.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein an upper surface of the gate dielectric layer is even with an upper surface of the work function layer.

### Claim 8

A semiconductor device, comprising:
a gate stack over a semiconductor substrate, the gate stack comprising a gate dielectric layer, a work function layer, and a conductive fill layer, the work function layer extending along opposing sides and a bottom of the conductive fill layer, the gate dielectric layer extending along sidewalls and a bottom of the work function layer, a topmost surface of the conductive fill layer being above a topmost surface of the work function layer and a topmost surface of the gate dielectric layer in a cross-sectional view;
a cap element over the gate stack, a portion of the cap element extending below the topmost surface of the conductive fill layer, the portion of the cap element comprising a dielectric material;
a spacer element having a first portion extending along a sidewall of the gate stack and a second portion extending along a sidewall of the cap element, the first portion of the spacer element having a first width, the second portion of the spacer element having a second width, the first width being greater than the second width; and
a source/drain region extending into the semiconductor substrate, a top surface of the source/drain region being above a bottom surface of the work function layer.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein a width of the conductive fill layer does not increase above the topmost surface of the work function layer in the cross-sectional view.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the conductive fill layer has a sidewall extending from the topmost surface of the work function layer to the topmost surface of the conductive fill layer in the cross-sectional view, an entirety of the sidewall of the conductive fill layer being linear.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein a sidewall of the cap element has a lower portion with a first uniform slope and an upper portion with a second uniform slope, the second uniform slope being less than the first uniform slope, the upper portion of the sidewall of the cap element extending from the lower portion of the sidewall of the cap element to a topmost surface of the cap element.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein a width of the cap element at the topmost surface of the conductive fill layer is in a range between 25 nm and 35 nm in the cross-sectional view.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, wherein a width of the cap element at a topmost surface of the cap element is in a range between 27 nm and 37 nm in the cross-sectional view.

### Claim 14 (depends on 8)

The semiconductor device of claim 8, wherein the cap element comprises silicon nitride or silicon oxynitride, and wherein the spacer element comprises silicon nitride, silicon oxynitride, or silicon oxide.

### Claim 15

A semiconductor device, comprising:
a gate stack over a semiconductor substrate, the gate stack comprising a work function layer and a conductive fill layer, the work function layer extending along sidewalls and a bottommost surface of the conductive fill layer, a topmost surface of the conductive fill layer being above a topmost surface of the work function layer in a cross-sectional view;
a cap element over the gate stack, a dielectric material of the cap element being in physical contact with the topmost surface of the work function layer, a width of the cap element increasing as the cap element extends away from the topmost surface of the conductive fill layer and toward a topmost surface of the cap element;
a spacer element on a sidewall of the cap element and a sidewall of the gate stack, wherein the spacer element has an inner sidewall facing the gate stack and the cap element, the inner sidewall having a lower portion with a first slope and an upper portion with a second slope, the second slope being less than the first slope, wherein the upper portion of the inner sidewall extends from the lower portion of the inner sidewall to a topmost surface of the spacer element, wherein at least a portion of the lower portion is above the topmost surface of the conductive fill layer in the cross-sectional view; and
a source/drain region extending into the semiconductor substrate, a top surface of the source/drain region being above a top surface of the semiconductor substrate.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein a width of the conductive fill layer above the work function layer is no wider than a width of the conductive fill layer contacting the work function layer.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the gate stack further comprises a gate dielectric layer, a portion of the gate dielectric layer extending along the inner sidewall of the spacer element, the topmost surface of the conductive fill layer being above a topmost surface of the gate dielectric layer.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the topmost surface of the gate dielectric layer is level with the topmost surface of the work function layer.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein the cap element is in physical contact with the topmost surface of the gate dielectric layer and the topmost surface of the work function layer.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, wherein the gate stack further comprises a gate dielectric layer, an upper surface of the gate dielectric layer is lower than an upper surface of the spacer element.