# US 12,002,871 B2 · Semiconductor device structure with work function layer and method for forming the same

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- Number: US 12,002,871 B2
- Document ID: US12002871B2
- Status: Granted
- Kind: B2
- Application number: 18/079,534
- Filed: 2022-12-12
- Published: 2023-04-13
- Granted: 2024-06-04
- Earliest claimed: 2014-10-08
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Wen-Han Fang; Chang-Yin Chen; Ming-Chia Tai; Po-Chi Wu
- Web page: https://patentgrep.com/patent/US12002871B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/853: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for forming a semiconductor device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate. The method includes forming a dielectric layer over the substrate, the first fin structure, and the second fin structure. The method includes forming a first work function layer in the first trench and the second trench. The method includes forming a first mask layer over the first work function layer in the first trench. The method includes removing the first work function layer exposed by the first mask layer. The method includes removing the first mask layer. The method includes forming a first gate electrode in the first trench and a second gate electrode in the second trench. The method includes forming a first hard mask layer in the first trench and a second hard mask layer in the second trench.

## Claims

### Claim 1

A method for forming a semiconductor device structure, comprising:
forming a first fin structure and a second fin structure over a substrate;
forming a dielectric layer over the substrate, the first fin structure, and the second fin structure, wherein the dielectric layer has a first trench exposing a first portion of the first fin structure and a second trench exposing a second portion of the second fin structure;
forming a first work function layer in the first trench and the second trench;
forming a first mask layer over the first work function layer in the first trench;
removing the first work function layer exposed by the first mask layer;
removing the first mask layer;
forming a first gate electrode in the first trench and a second gate electrode in the second trench; and
forming a first hard mask layer in the first trench and a second hard mask layer in the second trench, wherein the first hard mask layer has a first concave curved bottom surface, and the first gate electrode is in direct contact with the first concave curved bottom surface.

### Claim 2 (depends on 1)

The method for forming the semiconductor device structure as claimed in claim 1, wherein the first gate electrode has a convex curved top surface facing the first concave curved bottom surface of the first hard mask layer.

### Claim 3 (depends on 1)

The method for forming the semiconductor device structure as claimed in claim 1, wherein the second hard mask layer has a second concave curved bottom surface.

### Claim 4 (depends on 3)

The method for forming the semiconductor device structure as claimed in claim 3, wherein the second gate electrode is in direct contact with the second concave curved bottom surface.

### Claim 5 (depends on 4)

The method for forming the semiconductor device structure as claimed in claim 4, wherein the second gate electrode has a convex curved top surface facing the second concave curved bottom surface of the second hard mask layer.

### Claim 6 (depends on 1)

The method for forming the semiconductor device structure as claimed in claim 1, wherein a first top surface of the first mask layer is substantially level with a second top surface of the first work function layer in the first trench after the removing of the first work function layer exposed by the first mask layer.

### Claim 7 (depends on 1)

The method for forming a semiconductor device structure as claimed in claim 1, wherein the forming of the first mask layer over the first work function layer in the first trench comprises:
forming a mask material layer over the first fin structure, the substrate, and the first work function layer;
forming a second mask layer over the mask material layer, wherein the second mask layer has an opening over the first trench; and
removing a second portion of the mask material layer in the first trench through the opening, wherein after the removal of the second portion, the mask material layer remained in the first trench forms the first mask layer, and the removing of the first mask layer comprises removing the second mask layer.

### Claim 8 (depends on 1)

The method for forming a semiconductor device structure as claimed in claim 1, further comprising:
before the formation of the first gate electrode and the second gate electrode, forming a second work function layer over the first work function layer, wherein the first gate electrode is formed over the second work function layer in the first trench, and the second gate electrode is formed over the second work function layer in the second trench.

### Claim 9 (depends on 8)

The method for forming the semiconductor device structure as claimed in claim 8, wherein the first gate electrode has a convex curved surface protruding beyond a topmost surface of the second work function layer and in direct contact with the first concave curved bottom surface of the first hard mask layer.

### Claim 10 (depends on 1)

The method for forming the semiconductor device structure as claimed in claim 1, wherein the second gate electrode is wider than the first gate electrode.

### Claim 11

A semiconductor device structure, comprising:
a substrate;
a first fin structure and a second fin structure disposed over the substrate;
a first gate stack disposed over the substrate and overlapping the first fin structure, wherein the first gate stack comprises a first gate dielectric layer, a first work function layer, a second work function layer, and a first gate electrode sequentially stacked over the first fin structure, and a first topmost surface of the second work function layer is higher than a second topmost surface of the first work function layer and is lower than a third topmost surface of the first gate dielectric layer; and
a second gate stack disposed over the substrate and overlapping the second fin structure, wherein the second gate stack is wider than the first gate stack.

### Claim 12 (depends on 11)

The semiconductor device structure as claimed in claim 11, wherein the second topmost surface of the first work function layer is lower than a fourth topmost surface of the second gate stack.

### Claim 13 (depends on 12)

The semiconductor device structure as claimed in claim 12, wherein the second gate stack comprises a second gate dielectric layer, a third work function layer, a fourth work function layer, and a second gate electrode sequentially stacked over the second fin structure.

### Claim 14 (depends on 13)

The semiconductor device structure as claimed in claim 13, wherein the second topmost surface of the first work function layer is lower than a fifth topmost surface of the third work function layer, and the first work function layer and the third work function layer are made of a same material.

### Claim 15 (depends on 13)

The semiconductor device structure as claimed in claim 13, wherein the second topmost surface of the first work function layer is lower than a fifth topmost surface of the fourth work function layer, and the second work function layer and the fourth work function layer are made of a same material.

### Claim 16

A semiconductor device structure, comprising:
a substrate;
a first fin structure and a second fin structure disposed over the substrate;
a first gate stack disposed over the substrate and overlapping the first fin structure, wherein the first gate stack comprises a first gate dielectric layer, a first work function layer, a second work function layer, and a first gate electrode, and the second work function layer covers a first topmost surface of the first work function layer and exposes an upper portion of a sidewall of the first gate dielectric layer; and
a second gate stack disposed over the substrate and overlapping the second fin structure, wherein the second gate stack comprises a second gate dielectric layer, a third work function layer, and a second gate electrode sequentially stacked over the second fin structure, and the second gate electrode is wider than the first gate electrode.

### Claim 17 (depends on 16)

The semiconductor device structure as claimed in claim 16, wherein the first topmost surface of the first work function layer is lower than a second topmost surface of the third work function layer.

### Claim 18 (depends on 17)

The semiconductor device structure as claimed in claim 17, wherein the first work function layer and the third work function layer have a substantially same thickness.

### Claim 19 (depends on 18)

The semiconductor device structure as claimed in claim 18, wherein the first work function layer and the third work function layer are made of a same material.

### Claim 20 (depends on 16)

The semiconductor device structure as claimed in claim 16, wherein the second gate stack further comprises a fourth work function layer over the third work function layer, and a second topmost surface of the third work function layer and a third topmost surface of the fourth work function layer are substantially coplanar.