# US 12,002,870 B2 · Method of manufacturing a transistor

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,002,870 B2
- Document ID: US12002870B2
- Status: Granted
- Kind: B2
- Application number: 18/076,117
- Filed: 2022-12-06
- Published: 2023-03-30
- Granted: 2024-06-04
- Earliest claimed: 2020-09-28
- Assignees: Paragraf Limited
- Applicants: Paragraf Limited
- Inventors: Thomas James Badcock; Robert Wallis; Ivor Guiney; Simon Thomas
- Web page: https://patentgrep.com/patent/US12002870B2

## CPC

- H10D 30/01: Manufacture or treatment
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 48/362: {Unipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunnelling transistors [RTT], bulk barrier transistors [BBT], planar doped barrier transistors [PDBT] or charge injection transistors [CHINT]}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/8303: {Diamond}
- H10D 62/882: {Graphene}
- H10D 64/647: {Schottky drain or source electrodes for IGFETs}
- H10P 50/00: Etching of wafers, substrates or parts of devices
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

There is provided a method of manufacturing a transistor, the method comprising: (a) providing a substrate having a semiconductor surface; (b) providing a graphene layer structure on a first portion of the semiconductor surface, wherein the graphene layer structure has a thickness of n graphene monolayers, wherein n is at least 2; (c) etching a first portion of the graphene layer structure to reduce the thickness of the graphene layer structure in said first portion to from n−1 to 1 graphene monolayers; (d) forming a layer of dielectric material on the first portion of the graphene layer structure; and (e) providing: a source contact on a second portion of the graphene layer structure; a gate contact on the layer of dielectric material; and a drain contact on a second portion of the semiconductor surface of the substrate.

## Claims

### Claim 1

A method of manufacturing a transistor, the method comprising:
(a) providing a substrate having a semiconductor surface;
(b) providing a graphene layer structure on a first portion of the semiconductor surface, wherein the graphene layer structure has a thickness of n graphene monolayers, wherein n is at least 2;
(c) etching a first portion of the graphene layer structure to reduce the thickness of the graphene layer structure in said first portion to from n−1 to 1 graphene monolayers;
(d) forming a layer of dielectric material on the first portion of the graphene layer structure; and
(e) providing:
a source contact on a second portion of the graphene layer structure;
a gate contact on the layer of dielectric material; and
a drain contact on a second portion of the semiconductor surface of the substrate, wherein the drain contact does not abut the first portion of the graphene layer structure, and wherein steps (c) and (d) are achieved simultaneously by PE-ALD or oxidation of the first portion of the graphene layer structure so as to reduce the thickness of the graphene layer structure in said first portion to n−1 graphene monolayers and form a dielectric layer thereon.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the graphene layer structure consists of the first and second portions, and the first portion of the graphene layer structure is thinner than the second portion of the graphene layer structure.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the layer of dielectric material is further formed on an adjacent semiconductor surface of the substrate thereby covering the edge of the first portion of the graphene layer structure.

### Claim 4 (depends on 1)

The method according to claim 1, wherein n is at least 3 and/or less than 50.

### Claim 5 (depends on 4)

The method according to claim 4, wherein n is less than 15.

### Claim 6 (depends on 4)

The method according to claim 4, wherein n is at least 3, and wherein in step (c) the first portion of the graphene layer structure is etched to reduce the thickness of the graphene layer structure in said first portion to 2 or fewer graphene monolayers.

### Claim 7 (depends on 4)

The method according to claim 4, wherein n is at least 4.

### Claim 8 (depends on 7)

The method according to claim 7, wherein n is at least 4, and wherein in step (c) the first portion of the graphene layer structure is etched to reduce the thickness of the graphene layer structure in said first portion to 3 or fewer graphene monolayers.

### Claim 9 (depends on 1)

The method according to claim 1, wherein in step (c) the first portion of the graphene layer structure is etched to reduce the thickness of the graphene layer structure in said first portion to 1 graphene monolayer.

### Claim 10 (depends on 1)

The method according to claim 1, wherein the step of etching comprises plasma etching and/or laser etching and/or atomic layer etching.

### Claim 11 (depends on 10)

The method according to claim 10, wherein the step of etching comprises atomic layer etching.

### Claim 12 (depends on 1)

The method according to claim 1, wherein the layer of dielectric material is provided by atomic layer deposition, physical vapour deposition.

### Claim 13 (depends on 12)

The method according to claim 12, wherein the layer of dielectric material is provided by electron beam deposition or thermal evaporation, chemical vapour deposition, plasma enhanced chemical vapour deposition or metal organic chemical vapour deposition.

### Claim 14 (depends on 1)

The method according to claim 1, wherein the thickness of the layer of dielectric material is from 1 nm to 300 nm.

### Claim 15 (depends on 14)

The method according to claim 14, wherein the thickness of the layer of dielectric material is from 1 nm to 100 nm.

### Claim 16 (depends on 1)

The method according to claim 1, wherein the graphene layer structure is provided on a substrate by MOCVD or CVD, and/or wherein the step of providing the graphene layer structure comprises:
providing the substrate on a heated susceptor in a reaction chamber, the chamber having a plurality of cooled inlets arranged so that, in use, the inlets are distributed across the substrate and have constant separation from the substrate;
supplying a flow comprising a carbon-containing precursor compound through the inlets and into the reaction chamber to thereby decompose the precursor compound and form the graphene layer structure on the substrate,
wherein the inlets are cooled to less than 100° C. and the susceptor is heated to a temperature of at least 50° C. in excess of a decomposition temperature of the precursor.

### Claim 17 (depends on 1)

The method according to claim 1, wherein the graphene layer structure is a doped graphene layer structure.

### Claim 18 (depends on 17)

The method according to claim 17, wherein the graphene layer structure is doped with one or more elements selected from the group consisting of silicon, magnesium, zinc, arsenic, oxygen, boron, bromine and nitrogen.

### Claim 19 (depends on 1)

The method according to claim 1, wherein the substrate comprises elemental silicon and/or a III-V semiconductor compound.

### Claim 20 (depends on 19)

The method according to claim 19, wherein the substrate is silicon or a III-V semiconductor compound.

### Claim 21 (depends on 1)

The method according to claim 1, wherein the method further comprises connecting the transistor into an electronic circuit via the three contacts.

### Claim 22 (depends on 1)

The method according to claim 1, wherein n is 2 or 3.