# US 12,002,869 B2 · Gate contact structures and cross-coupled contact structures for transistor devices

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- Number: US 12,002,869 B2
- Document ID: US12002869B2
- Status: Granted
- Kind: B2
- Application number: 17/901,887
- Filed: 2022-09-02
- Published: 2022-12-29
- Granted: 2024-06-04
- Earliest claimed: 2017-10-24
- Assignees: GlobalFoundries U.S. Inc.
- Applicants: GlobalFoundries U.S. Inc.
- Inventors: Ruilong Xie; Youngtag Woo; Daniel Chanemougame; Bipul C. Paul; Lars W. Liebmann; Heimanu Niebojewski; Xuelian Zhu; Lei Sun; Hui Zang
- Web page: https://patentgrep.com/patent/US12002869B2

## CPC

- H10D 64/668: {the layer being a silicide, e.g. TiSi2}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/721: {having a gate-to-body connection, i.e. bulk dynamic threshold voltage IGFET (TFTs having gate-to-body connection H10D30/6708)}
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/0696: {by using sacrificial placeholders, e.g. using sacrificial plugs}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/076: {in via holes or trenches}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

## Claims

### Claim 1

An integrated circuit (IC) product, comprising:
a first conductive source/drain contact structure of a first transistor;
an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure, wherein the insulating source/drain cap physically contacts the upper surface of the first conductive source/drain contact structure;
a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor, wherein an upper surface of the GSD contact structure is positioned at a first level that is at a level that is below a level of an upper surface of the insulating source/drain cap, and wherein the GSD contact structure physically contacts a side surface of the insulating source/drain cap, a side surface of the first conductive source/drain contact structure, and a top surface of the first conductive source/drain contact structure; and
a gate contact structure that is conductively coupled to a second gate structure of a third transistor, the third transistor including a second conductive source/drain contact structure and a second insulating source/drain cap positioned above an upper surface of the second conductive source/drain contact structure, wherein the gate contact structure physically contacts an upper surface of the second insulating source/drain cap of the third transistor, wherein an upper surface of the gate contact structure is positioned at a second level that is at a level that is above the first level.

### Claim 2 (depends on 1)

The IC product of claim 1, further comprising:
a layer of insulating material comprising a first insulating material, wherein at least a portion of the gate contact structure is positioned within the layer of insulating material; and
an insulating cap positioned above the GSD contact structure, wherein at least a portion of the insulating cap is positioned in the layer of insulating material and wherein the insulating cap comprises a second insulating material that is different than the first insulating material.

### Claim 3 (depends on 2)

The IC product of claim 2, wherein the first insulating material comprises silicon dioxide and wherein the second insulating material comprises one of silicon nitride or a low-k insulating material.

### Claim 4 (depends on 2)

The IC product of claim 2, wherein at least a portion of the insulating cap is positioned over an upper surface of the insulating source/drain cap.

### Claim 5 (depends on 2)

The IC product of claim 2, further comprising a first conductive line that is positioned vertically above at least a portion of the GSD contact structure, wherein the first conductive line is conductively coupled to the gate contact structure and wherein at least a portion of the insulating cap is positioned vertically between the first conductive line and the GSD contact structure.

### Claim 6 (depends on 5)

The IC product of claim 5, wherein the first conductive line physically contacts an upper surface of the insulating cap.

### Claim 7 (depends on 1)

The IC product of claim 1, wherein a bottom surface of the GSD contact structure physically contacts an entirety of an upper surface of the first gate structure of the second transistor.

### Claim 8 (depends on 1)

The IC product of claim 1, further comprising a first sidewall spacer positioned adjacent the first gate structure of the second transistor, wherein a bottom surface of the GSD contact structure physically contacts an upper surface of the first sidewall spacer.

### Claim 9

An integrated circuit (IC) product, comprising:
a first conductive source/drain contact structure of a first transistor;
an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure, wherein the insulating source/drain cap physically contacts the upper surface of the first conductive source/drain contact structure;
a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor, wherein an upper surface of the GSD contact structure is positioned at a first level that is at a level that is below a level of an upper surface of the insulating source/drain cap, and wherein the GSD contact structure physically contacts a side surface of the first conductive source/drain contact structure, a top surface of the first conductive source/drain contact structure, and a side surface of the insulating source/drain cap;
an insulating cap positioned above the GSD contact structure; and
a gate contact structure that is conductively coupled to a second gate structure of a third transistor, the third transistor including a second conductive source/drain contact structure and a second insulating source/drain cap positioned above an upper surface of the second conductive source/drain contact structure, wherein the gate contact structure physically contacts an upper surface of the second insulating source/drain cap of the third transistor, wherein an upper surface of the gate contact structure is positioned at a second level that is at a level that is above the first level.

### Claim 10 (depends on 9)

The IC product of claim 9, further comprising a layer of insulating material comprising a first insulating material, wherein at least a portion of the gate contact structure is positioned within the layer of insulating material, wherein at least a portion of the insulating cap is positioned in the layer of insulating material and wherein the insulating cap comprises a second insulating material that is different than the first insulating material.

### Claim 11 (depends on 10)

The IC product of claim 10, wherein the first insulating material comprises silicon dioxide and wherein the second insulating material comprises one of silicon nitride or a low-k insulating material.

### Claim 12 (depends on 10)

The IC product of claim 10, wherein at least a portion of the insulating cap is positioned over an upper surface of the insulating source/drain cap.

### Claim 13 (depends on 9)

The IC product of claim 9, further comprising a first conductive line that is positioned vertically above at least a portion of the GSD contact structure, wherein the first conductive line is conductively coupled to the gate contact structure and wherein at least a portion of the insulating cap is positioned vertically between the first conductive line and the GSD contact structure.

### Claim 14 (depends on 13)

The IC product of claim 13, wherein the first conductive line physically contacts an upper surface of the insulating cap.

### Claim 15 (depends on 9)

The IC product of claim 9, wherein a bottom surface of the GSD contact structure physically contacts an entirety of an upper surface of the first gate structure of the second transistor.

### Claim 16 (depends on 9)

The IC product of claim 9, further comprising a first sidewall spacer positioned adjacent the first gate structure of the second transistor, wherein a bottom surface of the GSD contact structure physically contacts an upper surface of the first sidewall spacer.