# US 12,002,867 B2 · Contact structure for semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,867 B2 - Document ID: US12002867B2 - Status: Granted - Kind: B2 - Application number: 17/459,494 - Filed: 2021-08-27 - Published: 2023-03-02 - Granted: 2024-06-04 - Earliest claimed: 2021-08-27 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Chia-Hung Chu; Shuen-Shin Liang; Hsu-Kai Chang; Tzu Pei Chen; Kan-Ju Lin; Chien Chang; Hung-Yi Huang; Sung-Li Wang - Web page: https://patentgrep.com/patent/US12002867B2 ## CPC - H10D 64/62: Electrodes ohmically coupled to a semiconductor - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10D 30/024: {of fin field-effect transistors [FinFET]} - H10D 30/6219: {characterised by the source or drain electrodes} - H10D 64/01: Manufacture or treatment - H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10P 50/283: {by chemical means} - H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/42: Vias, e.g. via plugs - H10W 20/4432: {the principal metal being a noble metal, e.g. gold} - H10W 20/4441: {the principal metal being a refractory metal} - H10D 64/0112: {using conductive layers comprising silicides} - H10P 14/43: Chemical deposition, e.g. chemical vapour deposition [CVD] - H10W 20/056: {by filling conductive material into holes, grooves or trenches} - H10W 20/0698: {Local interconnections} - H10W 20/076: {in via holes or trenches} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a layer of dielectric material over the gate structure, a source/drain (S/D) contact layer formed through and adjacent to the gate structure, and a trench conductor layer over and in contact with the S/D contact layer. The S/D contact layer can include a layer of platinum-group metallic material and a silicide layer formed between the substrate and the layer of platinum-group metallic material. A top width of a top portion of the layer of platinum-group metallic material can be greater than or substantially equal to a bottom width of a bottom portion of the layer of platinum-group metallic material. ## Claims ### Claim 1 A method for forming a semiconductor structure, comprising: forming a source/drain (S/D) region over a substrate; forming a layer of dielectric material over the S/D region; forming a recess structure in the layer of dielectric material to expose the S/D region; depositing a first layer of metallic material in the recess structure at a first deposition rate and on a sidewall of the layer of dielectric material at a second deposition rate less than the first deposition rate, wherein the first layer of metallic material is in contact with the sidewall of the layer of dielectric material; and forming a second layer of metallic material over and in contact with the first layer of metallic material. ### Claim 2 (depends on 1) The method of claim 1, wherein forming the recess structure comprises forming the recess structure with a width from about 5 nm to about 20 nm. ### Claim 3 (depends on 1) The method of claim 1, wherein depositing the first layer of metallic material comprises depositing a platinum-group metallic material in the recess structure to seal the recess structure. ### Claim 4 (depends on 1) The method of claim 1, wherein depositing the first layer of metallic material comprises annealing the substrate with the deposited first layer of metallic material prior to forming the second layer of metallic material. ### Claim 5 (depends on 1) The method of claim 1, further comprising forming a silicide layer between the first layer of metallic material and the S/D region, wherein forming the silicide layer comprises forming a metal oxide layer over side surfaces of the recess structure. ### Claim 6 (depends on 5) The method of claim 5, further comprising performing an atomic layer etching process to selectively etch the metal oxide layer over the silicide layer. ### Claim 7 (depends on 1) The method of claim 1, further comprising forming a gate structure adjacent to the S/D region, wherein forming the second layer of metallic material comprises forming the second layer of metallic material over and in contact with the gate structure. ### Claim 8 (depends on 1) The method of claim 1, further comprising forming an additional layer of dielectric material on the layer of dielectric material and the first layer of metallic material prior to forming the second layer of metallic material, wherein the second layer of metallic material extends through the layer of dielectric material and the additional layer of dielectric material. ### Claim 9 (depends on 1) The method of claim 1, further comprising planarizing top surfaces of the layer of dielectric material and the first layer of metallic material prior to forming the second layer of metallic material. ### Claim 10 (depends on 5) The method of claim 5, wherein forming the silicide layer comprises depositing a third layer of metallic material in the recess structure and on the layer of dielectric material, wherein the third layer of metallic material is in contact with the S/D region. ### Claim 11 (depends on 1) The method of claim 1, wherein forming the second layer of metallic material comprises depositing a platinum-group metallic material on the first layer of metallic material. ### Claim 12 A method, comprising: forming a transistor on a substrate, wherein the transistor comprises a source/drain (S/D) region and a gate structure; forming a layer of dielectric material on the transistor; forming a recess structure in the layer of dielectric material to expose the S/D region; forming a silicide layer on the S/D region in the recess structure, wherein forming the silicide layer comprises forming a metal oxide layer over side surfaces of the recess structure; depositing a first layer of metallic material on the silicide layer at a first deposition rate and on the side surfaces of the recess structure at a second deposition rate, wherein the first deposition rate is greater than the second deposition rate; and forming a second layer of metallic material on the first layer of metallic material. ### Claim 13 (depends on 12) The method of claim 12, wherein depositing the first layer of metallic material comprises filling the recess structure with a platinum-group metallic material. ### Claim 14 (depends on 12) The method of claim 12, further comprising annealing, prior to forming the second layer of metallic material, the deposited first layer of metallic material at a temperature ranging from about 300° C. to about 500° C. ### Claim 15 (depends on 12) The method of claim 12, further comprising: depositing a third layer of metallic material in the recess structure prior to depositing the first layer of metallic material; annealing the third layer of metallic material to form a silicide layer on the S/D region and a metal oxide layer on the first layer of dielectric material; and removing the metal oxide layer on the layer of dielectric material with an atomic layer etching process. ### Claim 16 (depends on 12) The method of claim 12, wherein forming the second layer of metallic material comprises forming the second layer of metallic material extending through the layer of dielectric material and in contact with the gate structure. ### Claim 17 A method, comprising: forming a source/drain (S/D) region between first and second gate structures on a substrate; forming a layer of dielectric material on the S/D region and the first and second gate structures; forming a recess structure extending through the layer of dielectric material to expose the S/D region; depositing a first layer of metallic material on the S/D region at a first deposition rate and on a sidewall of the layer of dielectric material at a second deposition rate, wherein the first deposition rate is greater than the second deposition rate; and forming a second layer of metallic material on the first layer of metallic material. ### Claim 18 (depends on 17) The method of claim 17, wherein depositing the first layer of metallic material comprises filling the recess structure with a platinum-group metallic material. ### Claim 19 (depends on 17) The method of claim 17, further comprising annealing, prior to forming the second layer of metallic material, the deposited first layer of metallic material at a temperature ranging from about 300° C. to about 500° C. ### Claim 20 (depends on 17) The method of claim 17, further comprising: depositing a third layer of metallic material in the recess structure prior to depositing the first layer of metallic material; annealing the third layer of metallic material to form a silicide layer on the S/D region and a metal oxide layer on the layer of dielectric material; and removing the metal oxide layer on the layer of dielectric material with an atomic layer etching process.