# US 12,002,865 B2 · Interconnect features with sharp corners and method forming same

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- Number: US 12,002,865 B2
- Document ID: US12002865B2
- Status: Granted
- Kind: B2
- Application number: 17/326,848
- Filed: 2021-05-21
- Published: 2022-09-29
- Granted: 2024-06-04
- Earliest claimed: 2021-03-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Tze-Liang Lee
- Web page: https://patentgrep.com/patent/US12002865B2

## CPC

- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/01: Manufacture or treatment
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes depositing a dielectric layer, depositing a plurality of mandrel strips over the dielectric layer, and forming a plurality of spacers on sidewalls of the plurality of mandrel strips to form a plurality of mask groups. Each of the plurality of mandrel strips and two of the plurality of spacers form a mask group in the plurality of mask groups. The method further includes forming a mask strip connecting two neighboring mask groups in the plurality of mask groups, using the plurality of mask groups and the mask strip collectively as an etching mask to etch the dielectric layer and to form trenches in the dielectric layer, and filling a conductive material into the trenches to form a plurality of conductive features.

## Claims

### Claim 1

A method comprising:
depositing a dielectric layer;
depositing a plurality of mandrel strips over the dielectric layer;
forming a plurality of spacers on sidewalls of the plurality of mandrel strips to form a plurality of mask groups, wherein each of the plurality of mandrel strips and two of the plurality of spacers form a mask group in the plurality of mask groups;
forming a mask strip connecting two neighboring mask groups in the plurality of mask groups;
reducing a top surface of the mask strip to be level with or lower than top surfaces of the plurality of mask groups, wherein the reducing the top surface of the mask strip comprises:
polishing the mask strip; and
after the polishing, etching down the mask strip;
using the plurality of mask groups and the mask strip collectively as an etching mask to etch the dielectric layer, and to form trenches in the dielectric layer; and
filling a conductive material into the trenches to form a plurality of conductive features.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming the plurality of spacers comprises depositing a blanket layer, and performing an anisotropic etching process on the blanket layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the forming the mask strip comprises:
depositing a template layer over the plurality of mask groups, wherein the template layer has a top surface higher than the top surfaces of the plurality of mask groups;
forming an opening in the template layer, wherein at least two of the plurality of mask groups are revealed through the opening;
filling the opening to form the mask strip; and
removing the template layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the plurality of conductive features have lengthwise directions aligned to a straight line, and the plurality of conductive features comprises an end strip comprising a first end and a second end, wherein the first end is curved and has a first radius, and the second end is curved and has a second radius smaller than the first radius.

### Claim 5 (depends on 4)

The method of claim 4, wherein a ratio of the first radius to the second radius is greater than about 2.0.

### Claim 6 (depends on 1)

The method of claim 1, wherein the depositing the dielectric layer comprises depositing a low-k dielectric layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the top surface of the mask strip is reduced to be level with the top surfaces of the plurality of mask groups.

### Claim 8 (depends on 1)

The method of claim 1, wherein the top surface of the mask strip is reduced to be lower than the top surfaces of the plurality of mask groups.

### Claim 9 (depends on 5)

The method of claim 5, wherein the ratio of the first radius to the second radius is greater than about 3.0.

### Claim 10 (depends on 4)

The method of claim 4, wherein the first end is continuously curved, and the second end comprises two curved corner portions and a substantially straight portion connected the two curved corner portions.

### Claim 11

A method comprising:
forming a dielectric layer;
etching the dielectric layer to form openings; and
forming a plurality of conductive features, with at least upper portions of the conductive features filling the openings in the dielectric layer, wherein the plurality of conductive features have lengthwise directions aligned to a same straight line, wherein the plurality of conductive features comprise a first end feature, a second end feature, and at least one middle conductive feature between, and physically separated from, the first end feature and the second end feature, and the first end feature comprising:
a first end facing away from the second end feature, wherein the first end have first corners; and
a second end facing toward the second end feature, wherein the second end have second corners sharper than the first corners.

### Claim 12 (depends on 11)

The method of claim 11, further comprising forming an etching mask comprising:
a spacer forming a ring encircling an additional opening, the spacer comprising a first material; and
a mask strip separating the opening into a first portion and a second portion, wherein the mask strip is formed of a second material different from the first material; and
etching the dielectric layer to transfer the first portion and the second portion of the opening into the dielectric layer, wherein the spacer and the mask strip are used collectively as parts of a corresponding etching mask.

### Claim 13 (depends on 12)

The method of claim 12, wherein the spacer has a first height, and the mask strip has a second height lower than the first height.

### Claim 14 (depends on 12)

The method of claim 12, wherein the spacer encircle a mandrel, and the mandrel is also a part of the corresponding etching mask.

### Claim 15

A method comprising:
depositing a dielectric layer;
depositing a plurality of mandrel strips over the dielectric layer;
forming a plurality of spacers on sidewalls of the plurality of mandrel strips to form a plurality of mask groups, wherein each of the plurality of mandrel strips and two of the plurality of spacers form a mask group in the plurality of mask groups;
forming a mask strip connecting two neighboring mask groups in the plurality of mask groups, wherein the forming the mask strip comprises:
depositing a template layer over the plurality of mask groups, wherein the template layer has a top surface higher than top surfaces of the plurality of mask groups;
forming an opening in the template layer, wherein at least two of the plurality of mask groups are revealed through the opening;
filling the opening to form the mask strip; and
removing the template layer;
using the plurality of mask groups and the mask strip collectively as an etching mask to etch the dielectric layer, and to form trenches in the dielectric layer; and
filling a conductive material into the trenches to form a plurality of conductive features.

### Claim 16 (depends on 15)

The method of claim 15, wherein the forming the plurality of spacers comprises depositing a blanket layer, and performing an anisotropic etching process on the blanket layer.

### Claim 17 (depends on 15)

The method of claim 15, further comprising, reducing a top surface of the mask strip to be level with or lower than the top surfaces of the plurality of mask groups.

### Claim 18 (depends on 17)

The method of claim 17, wherein the top surface of the mask strip is reduced to be level with top surfaces of the plurality of mask groups.

### Claim 19 (depends on 17)

The method of claim 17, wherein the reducing the top surface of the mask strip comprises:
polishing the mask strip; and
after the polishing, etching-down the mask strip.

### Claim 20 (depends on 15)

The method of claim 15, wherein the plurality of conductive features have lengthwise directions aligned to a straight line, and the plurality of conductive features comprises an end strip comprising a first end and a second end, wherein the first end is curved and has a first radius, and the second end is curved and has a second radius smaller than the first radius.