# US 12,002,863 B2 · Semiconductor device with air-gap spacers

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- Number: US 12,002,863 B2
- Document ID: US12002863B2
- Status: Granted
- Kind: B2
- Application number: 17/462,484
- Filed: 2021-08-31
- Published: 2023-03-02
- Granted: 2024-06-04
- Earliest claimed: 2021-08-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Kai-Hsuan Lee; Chen-Ming Lee; Fu-Kai Yang; Mei-Yun Wang; Yen-Ming Chen
- Web page: https://patentgrep.com/patent/US12002863B2

## CPC

- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 30/0195: {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/509: {characterised by the material of the inner spacers}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/679: {comprising air gaps}
- H10D 64/687: {having cavities, e.g. porous gate dielectrics having gasses therein}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A method includes forming a gate structure on a substrate, forming a seal spacer covering a sidewall of the gate structure, forming a sacrificial spacer covering a sidewall of the seal spacer, forming source/drain regions sandwiching a channel region that is under the gate structure, and depositing a contact etch stop layer covering a sidewall of the sacrificial spacer. The method further includes removing the sacrificial spacer to form a trench, wherein the trench exposes a sidewall of the contact etch stop layer and the sidewall of the seal spacer, and depositing an inter-layer dielectric layer, wherein the inter-layer dielectric layer caps the trench, thereby defining an air gap inside the trench.

## Claims

### Claim 1

A method, comprising:
forming a sacrificial gate stack on a substrate;
depositing a sacrificial spacer layer, the sacrificial spacer layer having a vertical portion over sidewalls of the sacrificial gate stack and a horizontal portion over the substrate;
depositing a first dielectric layer covering the horizontal portion and the vertical portion of the sacrificial spacer layer;
patterning the first dielectric layer and the sacrificial spacer layer, thereby exposing a sidewall of the horizontal portion of the sacrificial spacer layer;
removing the horizontal portion and the vertical portion of the sacrificial spacer layer by an etching process through the exposed sidewall, thereby forming an air gap under the first dielectric layer; and
depositing a second dielectric layer along sidewalls of the first dielectric layer, thereby sealing the air gap.

### Claim 2 (depends on 1)

The method of claim 1, wherein the air gap has an L-shape.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
prior to the patterning of the first dielectric layer and the sacrificial spacer layer, replacing the sacrificial gate stack with a metal gate stack.

### Claim 4 (depends on 3)

The method of claim 3, wherein a top surface of the metal gate stack is below a top surface of the air gap.

### Claim 5 (depends on 3)

The method of claim 3, wherein a top surface of the metal gate stack is substantially leveled with a top surface of air gap.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
prior to the depositing of the sacrificial spacer layer, depositing a seal spacer along the sidewalls of the sacrificial gate stack, wherein after the air gap is formed a vertical portion of the air gap expands horizontally from the first dielectric layer to the seal spacer.

### Claim 7 (depends on 6)

The method of claim 6, wherein after the air gap is formed a horizontal portion of the air gap expands horizontally from the second dielectric layer to the seal spacer.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
prior to the depositing of the first dielectric layer, recessing the vertical portion of the sacrificial spacer layer to a position below a top surface the sacrificial gate stack.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
forming a source/drain feature over the substrate, wherein a top surface of the source/drain feature is exposed in the air gap.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
forming a source/drain contact over the source/drain feature, wherein the first and second dielectric layers are interposing the air gap and the source/drain contact.

### Claim 11

A method of forming a semiconductor device, comprising:
forming a fin protruding from a substrate;
forming a gate stack over the fin;
forming a seal spacer on a sidewall of the gate stack;
depositing a sacrificial spacer layer on a sidewall of the seal spacer and on a top surface of the fin;
depositing a first dielectric layer over the sacrificial spacer layer;
depositing a second dielectric layer over the first dielectric layer;
etching the second dielectric layer, the first dielectric layer, and the sacrificial spacer layer, thereby forming a trench exposing a bottom portion of the sacrificial spacer layer;
removing the sacrificial spacer layer by applying an etchant in the trench, thereby forming an air gap with an opening at a bottom portion of the trench; and
depositing a third dielectric layer in the trench, thereby sealing the opening of the air gap.

### Claim 12 (depends on 11)

The method of claim 11, wherein the air gap exposes the top surface of the fin.

### Claim 13 (depends on 12)

The method of claim 12, wherein the etching of the sacrificial spacer layer forms a dip in the top surface of the fin.

### Claim 14 (depends on 11)

The method of claim 11, further comprising:
forming a source/drain feature over the fin, wherein the trench exposes the source/drain feature, and wherein the air gap exposes a top surface of the source/drain feature.

### Claim 15 (depends on 11)

The method of claim 11, wherein the gate stack is a dummy gate stack, further comprising:
removing the dummy gate stack, thereby forming a gate trench;
forming a metal gate stack in the gate trench, wherein a top surface of the metal gate stack is below a top surface of the air gap; and
forming a gate capping layer over the top surface of the metal gate stack.

### Claim 16 (depends on 15)

The method of claim 15, wherein a top surface of the gate capping layer is below the top surface of the air gap.

### Claim 17

A method of forming a semiconductor device, comprising:
forming a fin protruding from a substrate;
forming a sacrificial gate stack across the fin;
forming a gate spacer layer on sidewalls of the sacrificial gate stack;
growing an epitaxial feature adjacent the gate spacer layer;
after the growing of the epitaxial feature, thinning the gate spacer layer;
depositing a sacrificial layer on sidewalls of the gate spacer layer and on a top surface of the epitaxial feature;
depositing a first dielectric layer over the sacrificial spacer layer;
replacing the sacrificial gate stack with a metal gate stack;
etching the first dielectric layer and the sacrificial layer to expose a sidewall of the sacrificial layer;
removing the sacrificial layer to form an air gap under the first dielectric layer; and
depositing a second dielectric layer on sidewalls of the first dielectric layer, wherein the second dielectric layer seals the air gap.

### Claim 18 (depends on 17)

The method of claim 17, wherein the etching of the first dielectric layer and the sacrificial layer is after the replacing of the sacrificial gate stack.

### Claim 19 (depends on 17)

The method of claim 17, further comprising:
prior to the depositing of the first dielectric layer, partially removing a vertical portion of the sacrificial layer from the sidewalls of the gate spacer layer.

### Claim 20 (depends on 17)

The method of claim 17, wherein the top surface of the epitaxial feature is exposed in the air gap.