# US 12,002,862 B2 · Inter-level handshake for dense 3D logic integration

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,002,862 B2
- Document ID: US12002862B2
- Status: Granted
- Kind: B2
- Application number: 17/328,289
- Filed: 2021-05-24
- Published: 2022-06-09
- Granted: 2024-06-04
- Earliest claimed: 2020-12-04
- Assignees: Tokyo Electron Limited
- Applicants: Tokyo Electron Limited
- Inventors: Lars Liebmann; Jeffrey Smith; Daniel Chanemougame; Paul Gutwin
- Web page: https://patentgrep.com/patent/US12002862B2

## CPC

- H10D 30/6729: {characterised by the electrodes}
- H10D 89/10: Integrated device layouts
- H10B 10/125: {the MOSFET being a thin film transistor [TFT]}
- H10B 10/18: {Peripheral circuit regions}
- H10D 30/0198: {forming source or drain electrodes wherein semiconductor bodies are replaced by dielectric layers and the source or drain electrodes extend through the dielectric layers}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6715: {characterised by the doping profiles, e.g. having lightly-doped source or drain extensions}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 88/00: Three-dimensional [3D] integrated devices
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device includes a first device plane over a substrate. The first device plane includes a first transistor device having a first source/drain (S/D) region formed in an S/D channel. A second device plane is formed over the first device plane. The second device plane includes a second transistor device having a second gate formed in a gate channel which is adjacent to the S/D channel. A first inter-level connection is formed from the first S/D region of the first transistor device to the second gate of the second transistor device. The first inter-level connection includes a lateral offset from the S/D channel to the gate channel.

## Claims

### Claim 1

A semiconductor device, comprising:
a first device plane over a substrate, the first device plane including a first transistor device having a first source/drain (S/D) region formed in an S/D channel;
a second device plane over the first device plane, the second device plane including a second transistor device having a second gate formed in a gate channel which is adjacent to the S/D channel; and
a first inter-level connection from the first S/D region of the first transistor device to the second gate of the second transistor device, wherein the first inter-level connection includes a lateral offset from the S/D channel to the gate channel, wherein
the first inter-level connection comprises the S/D channel, a horizontal portion that contacts the S/D channel, and a vertical portion that connects the horizontal portion to the second gate, and
the vertical portion extends from the first device plane to the second device plane and corresponds to a vertical distance from the first S/D region to the second gate relative to a surface of the substrate.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the horizontal portion corresponds to the lateral offset.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first inter-level connection has an L shape in a horizontal cross section parallel to a surface of the substrate.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first inter-level connection comprises a conductive metal wiring structure.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the first transistor device is configured to provide an input signal to the second transistor device.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising a second inter-level connection that connects a first gate of the first transistor device to a second S/D region in the second device plane.

### Claim 7 (depends on 2)

The semiconductor device of claim 2, wherein the second S/D region is part of the second transistor device in the second device plane.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, wherein the second S/D region is part of a third transistor device in the second device plane.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the first transistor device and the second transistor device are both complementary field-effect transistors (CFETs).

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein:
the first transistor device is an n-type field-effect transistor (FET),
the second transistor device is a p-type FET, and
the first device plane further includes another n-type FET so as to form a CFET with the second transistor device.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the vertical portion is in direct contact with the horizontal portion.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein the vertical portion is configured to electrically connect the horizontal portion to the second gate.

### Claim 13

A semiconductor device, comprising:
a pair of CFETs formed over a substrate, the pair of CFETs including an upper CFET positioned over a lower CFET, each CFET including a p-type FET and an n-type FET positioned over each other resulting in a vertical stack of at least four FETs relative to a surface of the substrate; and
an inter-level connection from a pair of complementary gates formed in a gate channel of one CFET to an S/D region formed in an S/D channel of the other CFET, wherein the gate channel of one CFET has a lateral offset from the S/D channel of the other CFET in a horizontal direction along the surface of the substrate and a vertical distance from the S/D channel of the other CFET in a vertical direction relative to the surface of the substrate.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the inter-level connection comprises:
the S/D channel;
a horizontal portion that is connected to the S/D channel and corresponds to the lateral offset, and
a vertical portion that connects the horizontal portion to the gate channel and corresponds to the vertical distance.

### Claim 15 (depends on 13)

The semiconductor device of claim 13, wherein a gate occupies a respective channel being recessed.

### Claim 16 (depends on 13)

The semiconductor device of claim 13, wherein the inter-level connection is formed from an upper pair of complementary gates of the upper CFET to a lower S/D region of the lower CFET, the semiconductor device further comprising a self-aligned contact that connects the upper pair of complementary gates to one or more structures positioned below the upper pair of complementary gates.