# US 12,002,860 B2 · Semiconductor device and fabrication method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,002,860 B2
- Document ID: US12002860B2
- Status: Granted
- Kind: B2
- Application number: 17/401,323
- Filed: 2021-08-13
- Published: 2023-02-16
- Granted: 2024-06-04
- Earliest claimed: 2021-08-13
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Oreste Madia; Georgios Vellianitis; Gerben Doornbos; Marcus Johannes Henricus Van Dal
- Web page: https://patentgrep.com/patent/US12002860B2

## CPC

- H10D 62/82: Heterojunctions
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 64/033: {comprising ferroelectric layers}
- H10D 64/689: {having ferroelectric layers}
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device is provided. The semiconductor device includes a gate layer, a semiconductor layer and a ferroelectric layer disposed between the gate layer and the semiconductor layer. The semiconductor layer includes a first material containing a Group III element, a rare-earth element and a Group VI element, the ferroelectric layer includes a second material containing a Group III element, a rare-earth element and a Group V element and the gate layer includes a third material containing a Group III element and a rare-earth element. A method of fabricating a semiconductor device is also provided.

## Claims

### Claim 1

A semiconductor device, comprising:
a gate layer;
a semiconductor layer;
a ferroelectric layer disposed between the gate layer and the semiconductor layer,
wherein the semiconductor layer includes a first material containing a Group III element, a rare-earth element and a Group VI element, the ferroelectric layer includes a second material containing a Group III element, a rare-earth element and a Group V element and the gate layer includes a third material containing a Group III element and a rare-earth element; and
source and drain terminals being in direct contact with the semiconductor layer, wherein a topmost position of an interface between the semiconductor layer and the ferroelectric layer is lower than top surfaces of the source and drain terminals, and
wherein a content of the rare-earth element in the semiconductor layer gradually varies from a first side of the semiconductor layer to a second side of the semiconductor layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the Group III element and the rare-earth element of the first material, the Group III element and the rare-earth element of the second material and the Group III element and the rare-earth element of the third material are respectively the same.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein first material comprises aluminum scandium oxycarbide (AlScOC), the second material comprises aluminum scandium nitride (AlScN) and the third material comprises aluminum scandium (AlSc) alloy.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the first material comprises AlScOC with a scandium (Sc) content ranging from about 10% to about 50%.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein the second material comprises AlScN with a scandium (Sc) content ranging from about 10% to about 60%.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the ferroelectric layer and the gate layer are in a reverse U shape, and the ferroelectric layer and the gate layer extends over a top surface and opposite side surfaces of the semiconductor layer.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the source and drain terminals are on opposite ends of the gate layer and the ferroelectric layer, and sidewalls of the gate layer and the ferroelectric layer are in-between sidewalls of the semiconductor layer.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the source and drain terminals and the gate layer are on opposite sides of the semiconductor layer, and the gate layer is disposed on an interconnect structure.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor device further comprises another interconnect structure dispose on and in direct contact with the source and drain terminals.

### Claim 10

A method of fabricating a semiconductor device, comprising:
providing a semiconductor substrate;
forming a layer stack structure over the semiconductor substrate, the layer stack structure includes a channel layer, a gate dielectric layer and a gate layer sequentially stacked over one another;
patterning the layer stack structure to form a gate structure; and
forming source and drain terminals over the channel layer, the source and drain terminals being in contact with the channel layer, wherein the channel layer includes a scandium-doped aluminum oxycarbide layer, the gate dielectric layer includes a scandium-doped aluminum nitride layer and the gate layer includes a scandium-doped aluminum layer, a scandium content in the channel layer gradually varies from a first side of the channel layer to a second side of the channel layer, and wherein top surfaces of the source and drain terminals are located at a position higher than a topmost interface of the gate dielectric layer and the channel layer.

### Claim 11 (depends on 10)

The method of claim 10, wherein the layer stack structure of the channel layer, the gate dielectric layer and the gate layer is in-situ formed in a single chamber.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein a content of the rare-earth element in the ferroelectric layer gradually varies from a first side of the ferroelectric layer to a second side of the ferroelectric layer.