# US 12,002,857 B2 · High electron mobility transistor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,857 B2 - Document ID: US12002857B2 - Status: Granted - Kind: B2 - Application number: 17/539,078 - Filed: 2021-11-30 - Published: 2023-06-01 - Granted: 2024-06-04 - Earliest claimed: 2021-11-30 - Assignees: Vanguard International Semiconductor Corporation - Applicants: Vanguard International Semiconductor Corporation - Inventors: Shin-Cheng Lin; Chia-Ching Huang - Web page: https://patentgrep.com/patent/US12002857B2 ## CPC - H10D 62/357: {of FETs} - H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs} - H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions - H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN} - H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)} - H10D 62/343: {Gate regions of field-effect devices having PN junction gates} - H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A high electron mobility transistor includes a substrate, a compound semiconductor stacked layer, a cap layer, a gate electrode, a source electrode, a drain electrode, and a buried electrode and/or a conductive structure. The substrate has an active area. The cap layer is disposed on the compound semiconductor stacked layer. The gate electrode is disposed on the cap layer and extends along a first direction. The source electrode and the drain electrode are disposed on the compound semiconductor stacked layer, respectively on two sides of the gate electrode, and arranged along a second direction, where the first direction is perpendicular to the second direction. The conductive structure and/or the buried electrode passes through the compound semiconductor stacked layer and surrounds or lies in the active area, where the conductive structure and/or the buried electrode has a constant electric potential or is grounded. ## Claims ### Claim 1 A high electron mobility transistor (HEMT), comprising: a substrate, including an active area; a compound semiconductor stacked layer, comprising a buffer layer, a high resistance layer, a channel layer, and a barrier layer disposed on the substrate in sequence; a cap layer, disposed on the compound semiconductor stacked layer; a gate electrode, disposed on the cap layer and extending along a first direction; a source electrode and a drain electrode, disposed on the compound semiconductor stacked layer, respectively disposed on two sides of the gate structure, and arranged along a second direction, wherein the first direction is perpendicular to the second direction; and a buried electrode, passing through the compound semiconductor stacked layer, disposed in the active area and configured to have a constant electric potential or be grounded, wherein the source electrode comprises a first portion and a second portion arranged along the first direction, the buried electrode is disposed between the first portion and the second portion, and the buried electrode is separated from the first portion and the second portion. ### Claim 2 (depends on 1) The high electron mobility transistor of claim 1, further comprising a semiconductor layer, disposed between the substrate and the compound semiconductor stacked layer, wherein the material of the semiconductor layer comprises silicon, gallium nitride, ceramic, silicon carbide, aluminum nitride, aluminum oxide, or a combination thereof. ### Claim 3 (depends on 2) The high electron mobility transistor of claim 2, further comprising a conductive structure, passing through the compound semiconductor stacked layer and surrounding the active area, wherein the conductive structure is configured to have a constant electric potential or be grounded. ### Claim 4 (depends on 3) The high electron mobility transistor of claim 3, wherein the buried electrode is electrically connected to the semiconductor layer, or the conductive structure is electrically connected to the semiconductor layer. ### Claim 5 (depends on 1) The high electron mobility transistor of claim 1, wherein the buried electrode is electrically connected to the source electrode through an interconnection structure. ### Claim 6 (depends on 1) The high electron mobility transistor of claim 1, further comprising a source metal pattern, disposed on the first portion and the second portion of the source electrode, wherein the buried electrode is disposed directly under the source metal pattern, and the buried electrode is electrically connected to the source electrode through the source metal pattern. ### Claim 7 (depends on 1) The high electron mobility transistor of claim 1, wherein the source electrode and the drain electrode pass through the barrier layer to a top surface of the channel layer, or into the channel layer. ### Claim 8 (depends on 1) The high electron mobility transistor of claim 1, wherein the substrate comprises a core substrate and a composite material layer wrapping around the core substrate. ### Claim 9 (depends on 8) The high electron mobility transistor of claim 8, wherein the core substrate comprises ceramic, silicon carbide, aluminum nitride or sapphire, and the composite material layer comprises an insulating material layer and a semiconductor material layer. ### Claim 10 A high electron mobility transistor (HEMT), comprising: a substrate, including an active area, wherein the active area comprises a plurality of repeating units; a compound semiconductor stacked layer, comprising a buffer layer, a high resistance layer, a channel layer, and a barrier layer disposed on the substrate in sequence; and a conductive structure, passing through the compound semiconductor stacked layer, surrounding the active area and configured to have a constant electric potential or be grounded, wherein at least one of the repeating units comprises: a cap layer, disposed on the compound semiconductor stacked layer; a gate electrode, disposed on the cap layer and extending along a first direction; and a source electrode and a drain electrode, disposed on the compound semiconductor stacked layer, respectively disposed on two sides of the gate electrode, and arranged along a second direction, wherein the first direction is perpendicular to the second direction. ### Claim 11 (depends on 10) The high electron mobility transistor of claim 10, further comprising a buried electrode, passing through the compound semiconductor stacked layer, disposed in the active area and configured to have a constant electric potential or be grounded. ### Claim 12 (depends on 11) The high electron mobility transistor of claim 11, wherein the conductive structure is separated from the source electrode, and the conductive structure is electrically connected to the source electrode through an interconnection structure. ### Claim 13 (depends on 10) The high electron mobility transistor of claim 10, further comprising a semiconductor layer, disposed between the substrate and the compound semiconductor stacked layer, wherein the material of the semiconductor layer comprises silicon, gallium nitride, ceramic, silicon carbide, aluminum nitride, aluminum oxide, or a combination thereof. ### Claim 14 (depends on 11) The high electron mobility transistor of claim 11, wherein the source electrode comprises a first portion and a second portion arranged along the first direction, the buried electrode is disposed between the first portion and the second portion, and the buried electrode is separated from the first portion and the second portion. ### Claim 15 (depends on 14) The high electron mobility transistor of claim 14, wherein the buried electrode is electrically connected to the source electrode through an interconnection structure. ### Claim 16 (depends on 14) The high electron mobility transistor of claim 14, further comprising a source metal pattern, disposed on the first portion and the second portion of the source electrode, wherein the buried electrode is disposed directly under the source metal pattern, and the buried electrode directly contacts the source metal pattern to be electrically connected to the source electrode. ### Claim 17 (depends on 10) The high electron mobility transistor of claim 10, wherein the at least one of the repeating units further comprises another gate electrode, the drain electrode is disposed between the gate electrode and the another gate electrode, or the source electrode is disposed between the gate electrode and the another gate electrode. ### Claim 18 (depends on 10) The high electron mobility transistor of claim 10, wherein the source electrode and the drain electrode pass through the barrier layer to a top surface of the channel layer, or into the channel layer. ### Claim 19 (depends on 10) The high electron mobility transistor of claim 10, wherein the substrate comprises a silicon-on-insulator substrate.