# US 12,002,856 B2 · Vertical field effect transistor with crosslink fin arrangement

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- Number: US 12,002,856 B2
- Document ID: US12002856B2
- Status: Granted
- Kind: B2
- Application number: 18/179,556
- Filed: 2023-03-07
- Published: 2023-06-29
- Granted: 2024-06-04
- Earliest claimed: 2020-12-17
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Indira Seshadri; Ruilong Xie; Chen Zhang; Ekmini Anuja De Silva
- Web page: https://patentgrep.com/patent/US12002856B2

## CPC

- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a semiconductor structure includes forming a first array of mandrels on a hardmask layer disposed on an uppermost surface of a semiconductor substrate. First sidewall image transfer spacers are formed on opposing longitudinal sidewalls of each mandrel in the first array of mandrels. A second array of mandrels is formed on the hardmask layer. Each mandrel in the second array of mandrels is laterally separated from each mandrel in the first array of mandrels by the first sidewall image transfer spacers. Second sidewall image transfer spacers are formed on opposing transversal sidewalls of the first array of mandrels and the second array of mandrels. Portions of the second sidewall image transfer spacers are selectively removed to define a crosslink fin pattern to be transferred to the semiconductor substrate.

## Claims

### Claim 1

A method of forming a semiconductor structure, comprising:
forming a first array of mandrels on a hardmask layer disposed on an uppermost surface of a semiconductor substrate;
forming first sidewall image transfer spacers on opposing longitudinal sidewalls of each mandrel in the first array of mandrels;
forming a second array of mandrels on the hardmask layer, each mandrel in the second array of mandrels being laterally separated from each mandrel in the first array of mandrels by the first sidewall image transfer spacers;
forming second sidewall image transfer spacers on opposing transversal sidewalls of the first array of mandrels and the second array of mandrels; and
selectively removing portions of the second sidewall image transfer spacers to define a crosslink fin pattern.

### Claim 2 (depends on 1)

The method of claim 1, wherein selectively removing the portions of the second sidewall image transfer spacers comprises:
forming an organic planarization layer substantially covering the first array of mandrels, the first sidewall image transfer spacers, the second array of mandrels, and the second sidewall image transfer spacers;
etching the organic planarization layer to form via openings on selected areas of the second sidewall image transfer spacer; and
removing the portions of the second sidewall image transfer spacer located on the selected areas through the via openings.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
transferring the crosslink fin pattern to the hardmask layer to form a plurality of fin structures, the crosslink fin pattern including one or more vertical regions extending in a direction perpendicular to the uppermost surface of the semiconductor substrate and parallel to one another, at least two vertical regions of the one or more vertical regions being connected by a horizontal region extending between the at least two vertical regions in a direction parallel to the uppermost surface of the semiconductor substrate.

### Claim 4 (depends on 3)

The method of claim 3, wherein the at least two vertical regions connected by the horizontal region defines a crosslink fin architecture in the semiconductor structure.

### Claim 5 (depends on 3)

The method of claim 3, wherein at least one of the one or more vertical regions not connected by the horizontal region defines a single fin architecture.

### Claim 6

A method of forming a semiconductor structure, comprising:
patterning a plurality of fin structures on an uppermost surface of a semiconductor substrate, each fin structure of the plurality of fin structures including n first regions extending perpendicular to the uppermost surface of the semiconductor substrate and n-1 second regions extending between and connecting each of the n first regions and parallel to the uppermost surface of the semiconductor substrate, wherein n≤1.

### Claim 7 (depends on 6)

The method of claim 6, wherein the plurality of fin structures on the uppermost surface of the semiconductor substrate includes one or more first regions extending in a direction perpendicular to the uppermost surface of the semiconductor substrate and parallel to one another, at least two of the one or more first regions being connected by a second region extending between the at least two of the one or more first regions in a direction parallel to the uppermost surface of the semiconductor substrate.

### Claim 8 (depends on 7)

The method of claim 7, wherein the at least two first regions connected by the second region defines a crosslink fin architecture in the semiconductor structure.

### Claim 9 (depends on 7)

The method of claim 7, wherein at least one of the one or more first regions not connected by the second region defines a single fin architecture.

### Claim 10 (depends on 7)

The method of claim 7, further comprising:
forming a first fin structure above the uppermost surface of the semiconductor substrate including:
a first vertical region extending perpendicular to the uppermost surface of the semiconductor substrate;
a second vertical region extending perpendicular to the uppermost surface of the semiconductor substrate, the second vertical region being laterally separated from the first vertical region; and
a first horizontal region extending between and connecting the first vertical region and the second vertical region, and parallel to the uppermost surface of the semiconductor substrate.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
forming a second fin structure above the uppermost surface of the semiconductor substrate including:
a third vertical region extending perpendicular to the uppermost surface of the semiconductor substrate;
a fourth vertical region extending perpendicular to the uppermost surface of the semiconductor substrate;
a fifth vertical region extending perpendicular to the uppermost surface of the semiconductor substrate, the third vertical region being laterally separated from the fourth vertical region, and the fourth vertical region being laterally separated from the fourth vertical region;
a second horizontal region extending between and connecting the third vertical region and the fourth vertical region, and parallel to the uppermost surface of the semiconductor substrate;
a third horizontal region extending between and connecting the fourth vertical region and the fifth vertical region, and parallel to the uppermost surface of the semiconductor substrate; and
forming a third fin structure above the uppermost surface of the semiconductor substrate including only one sixth vertical region extending perpendicular to the uppermost surface of the substrate, wherein the first fin structure, the second fin structure and the third fin structure are simultaneously patterned in the semiconductor substrate.

### Claim 12

A method of forming a semiconductor structure comprising:
forming a hardmask layer on an uppermost surface of a semiconductor substrate; and
transferring a pattern to the hardmask layer to define a plurality of fin structures on the uppermost surface of the semiconductor substrate, the plurality of fins structures including one or more vertical regions extending in a direction perpendicular to the uppermost surface of the semiconductor substrate and parallel to one another, at least two vertical regions of the one or more vertical regions being connected by a horizontal region extending between the at least two vertical regions in a direction parallel to the uppermost surface of the semiconductor substrate.

### Claim 13 (depends on 12)

The method of claim 12, wherein the two or more vertical regions connected by the horizontal region defines a crosslink fin architecture in the semiconductor structure.

### Claim 14 (depends on 12)

The method of claim 12, wherein at least one of the one or more vertical regions not connected to by the horizontal region defines a single fin architecture.

### Claim 15 (depends on 12)

The method of claim 12, further comprising:
forming a first array of mandrels on the hardmask layer; and
forming a second array of mandrels on the hardmask layer.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
forming first sidewall image transfer spacers on opposing longitudinal sidewalls of each of the first array of mandrels and the second array of mandrels; and
forming second sidewall image transfer spacers on opposing transversal sidewalls of each of the first array of mandrels and the second array of mandrels.

### Claim 17 (depends on 16)

The method of claim 16, wherein the first sidewall image transfer spacers include SiCO and the second sidewall image transfer spacers include Ti.

### Claim 18 (depends on 16)

The method of claim 16, further comprising:
forming an organic planarization layer substantially covering the first array of mandrels, the first sidewall image transfer spacers, the second array of mandrels, and the second sidewall image transfer spacers; and
etching the organic planarization layer to form via openings on selected areas of the second sidewall image transfer spacer.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
removing portions of the second sidewall image transfer spacer located on the selected areas through the via openings.

### Claim 20 (depends on 18)

The method of claim 18, further comprising:
removing the organic planarization layer.

### Claim 21 (depends on 18)

The method of claim 18, further comprising:
removing the first array of mandrels and the second array of mandrels selective to the first sidewall image transfer spacers and the second sidewall image transfer spacers.

### Claim 22 (depends on 16)

The method of claim 16, further comprising:
patterning the hardmask layer, wherein the patterning comprises transferring a pattern defined by the first sidewall image transfer spacers and the second sidewall image transfer spacers to the hardmask layer.

### Claim 23 (depends on 22)

The method of claim 22, further comprising:
removing the first sidewall image transfer spacers and the second sidewall image transfer spacers.

### Claim 24 (depends on 22)

The method of claim 22, further comprising:
using the patterned hardmask layer, etching the uppermost surface of the semiconductor substrate to form the plurality of fin structures.

### Claim 25 (depends on 22)

The method of claim 22, wherein the pattern defined by the first sidewall image transfer spacers and the second sidewall image transfer spacers comprises a combination of single and crosslink fin configurations.