# US 12,002,855 B2 · Method of manufacturing a semiconductor device and a semiconductor device

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- Number: US 12,002,855 B2
- Document ID: US12002855B2
- Status: Granted
- Kind: B2
- Application number: 18/075,172
- Filed: 2022-12-05
- Published: 2023-03-30
- Granted: 2024-06-04
- Earliest claimed: 2020-01-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Jui Fu Hsieh; Chih-Teng Liao; Chih-Shan Chen; Yi-Jen Chen; Tzu-Chan Weng
- Web page: https://patentgrep.com/patent/US12002855B2

## CPC

- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10P 50/242: {of Group IV materials}
- H10P 50/244: {comprising alternated and repeated etching and passivation steps}
- H10P 50/267: {using plasmas}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed by a plasma etching process. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, the plasma process comprises applying pulsed bias voltage and RF voltage with pulsed power.

## Claims

### Claim 1

A method of manufacturing a source/drain structure of a semiconductor device, the method comprising:
recessing, by a plasma etching process, a source/drain region of a semiconductor layer to form a recess; and
forming an epitaxial layer over the recess,
wherein the plasma etching process comprises applying pulsed bias voltage changing between a high voltage and a low voltage lower than the high voltage and RF voltage with pulsed power changing between a high power and a low power lower than the high power, and
when the pulsed bias voltage is the high voltage, the pulsed power is the low power.

### Claim 2 (depends on 1)

The method of claim 1, wherein the low voltage is zero.

### Claim 3 (depends on 1)

The method of claim 1, wherein a duty ratio of each of the pulsed bias voltage and the pulsed power is in a range from 70% to 90%.

### Claim 4 (depends on 1)

The method of claim 1, wherein a duty ratio of each of the pulsed bias voltage and the pulsed power is in a range from 40% to 60%.

### Claim 5 (depends on 1)

The method of claim 1, wherein a duty ratio of each of the pulsed bias voltage and the pulsed power is in a range from 10% to 30%.

### Claim 6 (depends on 1)

The method of claim 1, wherein the high voltage is in a range from 200 V to 400 V, and the low voltage is in a range from 100 V to 150 V.

### Claim 7 (depends on 1)

The method of claim 1, wherein the high power is in a range from 1000 W to 1500 W and the low power is in a range from 300 W to 500 W.

### Claim 8 (depends on 1)

The method of claim 1, wherein the plasma process comprises supplying HBr gas and one or more noble gases.

### Claim 9 (depends on 8)

The method of claim 8, wherein a flow ratio of the HBr gas and the one or more noble gases is in a range from 0.3 to 0.7.

### Claim 10 (depends on 8)

The method of claim 8, wherein a flow ratio of the HBr gas and the one or more noble gases is in a range from 0.4 to 0.6.

### Claim 11 (depends on 1)

The method of claim 1, wherein the plasma process is performed under a pressure in a range from 1 mTorr to 100 mTorr.

### Claim 12 (depends on 1)

The method of claim 1, wherein one cycle of the pulsed bias and the pulsed power having one high value time and one low value time is in a range from 0.5 sec to 20 sec.

### Claim 13

A semiconductor device comprising:
a fin structure disposed over a substrate;
a gate structure disposed over a part of the fin structure; and
a source/drain epitaxial layer over a source/drain region of the fin structure, wherein:
an interface between the source/drain epitaxial layer and the source/drain region of the fin structure has a W-shape having two deeper portions and one shallow portion disposed between the two deeper portions, the shallow portion having a smaller depth than the deeper portions.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein a depth of the shallow portion measured from a level of an interface between the gate structure and the fin structure is in a range from 50 nm to 70 nm.

### Claim 15 (depends on 13)

The semiconductor device of claim 13, wherein a depth of the deeper portions measured from a level of an interface between the gate structure and the fin structure is in a range from 45 nm to 65 nm.

### Claim 16 (depends on 13)

The semiconductor device of claim 13, wherein a difference between a depth at deeper one of the deeper portions and a depth at the shallow portion is in a range from 0.5 nm to 5 nm.

### Claim 17 (depends on 13)

The semiconductor device of claim 13, wherein when H1 is a depth of the shallow portion measured from a level of an interface between the gate structure and the fin structure and H2 is a depth of the deeper portions measured from the level of an interface between the gate structure and the fin structure, H1/H2 is in a range from 0.85 to 0.95.

### Claim 18

A semiconductor device comprising:
a semiconductor layer having a channel region;
a gate structure disposed over the channel region; and
a source/drain epitaxial layer over a source/drain region of the semiconductor layer, wherein:
an interface between the source/drain epitaxial layer and the source/drain region has a W-shape having two deeper portions and one shallow portion disposed between the two deeper portions, the shallow portion having a smaller depth than the deeper portions, and
when G1 is a thickness of the source/drain epitaxial layer corresponding to the shallow portion and G2 is a thickness of the source/drain epitaxial layer corresponding to one of the deeper portions, G1/G2 is in a range from 0.9 to 1.05.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein G1/G2 is in a range from 0.92 to 1.01.

### Claim 20 (depends on 18)

The semiconductor device of claim 18, wherein a height C1 of the source/drain epitaxial layer measured from a level of an interface between the gate structure and the channel region is in a range from 0.2 nm to 7 nm.