# US 12,002,853 B2 · Semiconductor device

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- Number: US 12,002,853 B2
- Document ID: US12002853B2
- Status: Granted
- Kind: B2
- Application number: 17/244,604
- Filed: 2021-04-29
- Published: 2021-12-02
- Granted: 2024-06-04
- Earliest claimed: 2020-05-29
- Assignees: Toyoda Gosei Co., Ltd.
- Applicants: Toyoda Gosei Co., Ltd.
- Inventors: Toru Oka; Tsutomu Ina
- Web page: https://patentgrep.com/patent/US12002853B2

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/149: {Source or drain regions of field-effect devices}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/80: characterised by the materials
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present invention provides a semiconductor device in which the contact resistance of the body electrode is reduced without reducing the channel mobility. The p-type layer is a Mg-doped p-GaN layer deposited on the first re-type layer. The p-type layer has a two-layer structure in which a first p-type layer and a second p-type layer are sequentially deposited. The second p-type layer has a Mg concentration higher than the Mg concentration of the first p-type layer. The recess is formed in a predetermined position on the surface of the second n-type layer, and has a depth passing through the second n-type layer and reaching the second p-type layer. The body electrode is formed on the bottom surface of the recess in contact with the p-type layer exposed thereon.

## Claims

### Claim 1

A semiconductor device as a transistor, having a semiconductor layer comprising Group III nitride semiconductor or gallium oxide-based semiconductor, the semiconductor device comprising:
a trench with an inner surface which is covered with a gate insulating film, the trench having a gate electrode therein;
a first n-type layer, a p-type layer, and a second n-type layer which are sequentially deposited;
a recess reaching the p-type layer from the surface of the second n-type layer; and
a body electrode in contact with the p-type layer exposed on a bottom surface of the recess,
wherein
the p-type layer comprises:
a third p-type layer disposed in contact with the first n-type layer;
a first p-type layer disposed in contact with the third p-type layer, the first p-type layer having an acceptor concentration lower than an acceptor concentration of the third p-type layer; and
a second p-type layer deposited on the first p-type layer, the second p-type layer having an acceptor concentration higher than the acceptor concentration of the first p-type layer and not lower than the acceptor concentration of the third p-type layer, and
the recess has a depth reaching the second p-type layer,
side surfaces of the third p-type layer, the first p-type layer, and the second p-type layer are in contact with a side surface of the gate insulating film, respectively, all of the side surfaces being a region serving as a channel of the transistor, and
a bottom surface of the body electrode is in contact with the second p-type layer exposed on the bottom surface of the recess.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the second p-type layer has a thickness of 0.05 μm to 0.2 μm.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the second p-type layer has an acceptor concentration of 1×1019/cm3 to 1×1020/cm3.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the depth of the recess is set so that the second p-type layer has a thickness of not less than 0.05 μm in a region under the recess.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the first p-type layer has an acceptor concentration of not more than 6×1018/cm3.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the third p-type layer has a thickness of 0.1 μm to 0.2 μm.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein the second p-type layer is the top layer of the p-type layer.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein the semiconductor device is a vertical semiconductor device having a trench gate structure.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein a distance between a bottom surface of the second n-type layer and the bottom surface of the body electrode is not less than 0 μm and not larger than 0.15 μm.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, wherein the first p-type layer has a thickness of 0.5 μm to 1.5 μm.