# US 12,002,850 B2 · Nanosheet-based semiconductor structure with dielectric pillar > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,850 B2 - Document ID: US12002850B2 - Status: Granted - Kind: B2 - Application number: 17/462,526 - Filed: 2021-08-31 - Published: 2023-03-02 - Granted: 2024-06-04 - Earliest claimed: 2021-08-31 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Kangguo Cheng; Julien Frougier; Ruilong Xie; Chanro Park - Web page: https://patentgrep.com/patent/US12002850B2 ## CPC - H10D 62/121: {oriented parallel to substrates} - H10D 84/0188: {Manufacturing their isolation regions} - H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors} - H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10D 84/0151: {Manufacturing their isolation regions} - H10D 84/0167: {Manufacturing their channels} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/8311: {the IGFETs characterised by having different channel structures} - H10D 84/85: Complementary IGFETs, e.g. CMOS - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ## Abstract A semiconductor structure includes a substrate, a first device disposed on the substrate and a second device disposed on the substrate. The first device includes a first plurality of nanosheets comprising a p-type material. The second device includes a second plurality of nanosheets comprising an n-type material. A dielectric isolation pillar is disposed between the first device and the second device. ## Claims ### Claim 1 A semiconductor structure comprising: a first device disposed on a substrate, the first device comprising a first plurality of nanosheets, wherein the first plurality of nanosheets comprises a p-type material; a second device disposed on the substrate, the second device comprising a second plurality of nanosheets, wherein the second plurality of nanosheets comprises an n-type material; a dielectric isolation pillar extending vertically from within a top surface of the substrate and disposed between the first device and the second device; a first shallow trench isolation region disposed at least partially within the substrate on a first lateral side of the first plurality of nanosheets; and a second shallow trench isolation region disposed at least partially within the substrate on a first lateral side of the second plurality of nanosheets; wherein a second lateral side of the first plurality of nanosheets extends from a first lateral side of the dielectric isolation pillar and a second lateral side of the second plurality of nanosheets extends from a second lateral side of the dielectric isolation pillar; wherein each of the first plurality of nanosheets are in a staggered arrangement relative to each of the second plurality of nanosheets; and wherein the first plurality of nanosheets and the second plurality of nanosheets are each of a uniform width. ### Claim 2 (depends on 1) The semiconductor structure according to claim 1 wherein the first plurality of nanosheets and the second plurality of nanosheets are in contact with the dielectric isolation pillar. ### Claim 3 (depends on 1) The semiconductor structure according to claim 1 wherein the p-type material comprises silicon germanium and wherein the n-type material comprise silicon. ### Claim 4 (depends on 1) The semiconductor structure according to claim 1 wherein the first device comprises a first given number of the first plurality of nanosheets and the second device comprises a second given number of the second plurality of nanosheets, wherein the first given number is different than the second given number. ### Claim 5 (depends on 4) The semiconductor structure according to claim 4 wherein the first given number of the first plurality of nanosheets is greater than the second given number of the second plurality of nanosheets. ### Claim 6 (depends on 5) The semiconductor structure according to claim 5 wherein the first plurality of nanosheets is vertical offset relative to the second plurality of nanosheets. ### Claim 7 (depends on 1) The semiconductor structure according to claim 1 wherein: the first device includes one or more gate structures each having a first work function metal, and source and drain regions; and the second device includes one or more gate structures each having a second work function metal, and source and drain regions. ### Claim 8 (depends on 7) The semiconductor structure according to claim 7 wherein the second work function metal is different from the first work function metal. ### Claim 9 (depends on 1) The semiconductor structure according to claim 1 including at least three gates disposed on the substrate. ### Claim 10 (depends on 1) The semiconductor structure according to claim 1 wherein the dielectric isolation pillar extends into the substrate a predetermined distance. ### Claim 11 A semiconductor structure comprising: a dielectric isolation pillar extending vertically from within a top surface of a substrate; a pFET device comprising a first plurality of channel nanosheets disposed on a first lateral side of the dielectric isolation pillar and in contacting relation therewith; an nFET device comprising a second plurality of channel nanosheets disposed on a second lateral side of the dielectric isolation pillar and in contacting relation therewith; a first shallow trench isolation region disposed at least partially within the substrate on a first lateral side of the pFET device; and a second shallow trench isolation region disposed at least partially within the substrate on a first lateral side of the nFET device; wherein a second lateral side of the pFET device extends from the first lateral side of the dielectric isolation pillar and a second lateral side of the nFET device extends from the second lateral side of the dielectric isolation pillar; wherein each of the first plurality of channel nanosheets are in a staggered arrangement relative to each of the second plurality of channel nanosheets; and wherein the first plurality of channel nanosheets and the second plurality of channel nanosheets are each of a uniform width. ### Claim 12 (depends on 11) The semiconductor structure according to claim 11 wherein the first plurality of channel nanosheets of the pFET device comprise a first material and the second plurality of channel nanosheets of the nFET device comprise a second material different from the first material. ### Claim 13 (depends on 12) The semiconductor structure according to claim 12 wherein the first material comprises silicon germanium and wherein the second material comprises silicon. ### Claim 14 (depends on 11) The semiconductor structure according to claim 11 wherein the pFET device includes a first number of channel nanosheets and the nFET device includes a second number of channel nanosheets different from the first number. ### Claim 15 (depends on 14) The semiconductor structure according to claim 14 wherein the first number of channel nanosheets of the pFET device is greater than the second number of channel nanosheets of the nFET device. ### Claim 16 (depends on 11) The semiconductor structure according to claim 11 wherein the channel nanosheets of the pFET device are vertically offset relative to the channel nanosheets of the nFET device. ### Claim 17 A method, comprising: forming a first device on a semiconductor substrate, the first device comprising a first plurality of nanosheets, wherein the first plurality of nanosheets comprises a p-type material; forming a second device on the semiconductor substrate, the second device comprising a second plurality of nanosheets, wherein the second plurality of nanosheets comprises an n-type material; forming a dielectric isolation pillar extending vertically from within a top surface of the semiconductor substrate between the first device and the second device; forming a first shallow trench isolation region at least partially within the semiconductor substrate on a first lateral side of the first plurality of nanosheets; and forming a second shallow trench isolation region at least partially within the semiconductor substrate on a first lateral side of the second plurality of nanosheets; wherein a second lateral side of the first plurality of nanosheets extends from a first lateral side of the dielectric isolation pillar and a second lateral side of the second plurality of nanosheets extends from a second lateral side of the dielectric isolation pillar; wherein each of the first plurality of nanosheets are in a staggered arrangement relative to each of the second plurality of nanosheets; and wherein the first plurality of nanosheets and the second plurality of nanosheets are each of a uniform width. ### Claim 18 (depends on 17) The method according to claim 17, wherein the p-type material of the first plurality of nanosheets comprises silicon germanium and the n-type material of the second plurality of nanosheets comprises silicon. ### Claim 19 (depends on 17) The method according to claim 17 including contacting each of the first plurality of nanosheets and the second plurality of nanosheets with the dielectric isolation pillar. ### Claim 20 (depends on 17) The method according to claim 17 including arranging the first plurality of nanosheets in vertical offset relation relative to the second plurality of nanosheets.