# US 12,002,845 B2 · Method of manufacturing a semiconductor device and a semiconductor device

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- Number: US 12,002,845 B2
- Document ID: US12002845B2
- Status: Granted
- Kind: B2
- Application number: 17/575,145
- Filed: 2022-01-13
- Published: 2023-01-26
- Granted: 2024-06-04
- Earliest claimed: 2021-07-23
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ting-Yeh Chen; Wei-Yang Lee; Chia-Pin Lin; Yuan-Ching Peng
- Web page: https://patentgrep.com/patent/US12002845B2

## CPC

- H10D 1/47: Resistors having no potential barriers
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/209: {of only resistors}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10W 44/401: {Resistive arrangements (H10W44/20, H10W42/80 take precedence)}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 62/852: being Group III-V materials comprising three or more elements, e.g. AlGaN or InAsSbP
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

In a method of manufacturing a semiconductor device, a fin structure, which includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, is formed. An isolation insulating layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer. The third dielectric layer is partially removed to form a trench. A fourth dielectric layer is formed by filling the trench with a dielectric material, thereby forming a wall fin structure.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
forming a fin structure including a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer;
forming an isolation insulating layer so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer;
forming a sacrificial cladding layer over at least sidewalls of the exposed hard mask layer and stacked layer;
forming a first dielectric layer over the sacrificial cladding layer;
forming a second dielectric layer made of a different material than the first dielectric layer over the first dielectric layer;
recessing the second dielectric layer;
forming a third dielectric layer made of a different material than the second dielectric layer over the recessed second dielectric layer;
partially removing the third dielectric layer to form a trench; and
forming a fourth dielectric layer by filling the trench with a dielectric material different from the third dielectric layer, thereby forming a wall fin structure.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first dielectric layer includes at least one of SiOC, SiOCN or SiCN.

### Claim 3 (depends on 1)

The method of claim 1, wherein the second dielectric layer includes at least one of silicon nitride, silicon oxide or SiON.

### Claim 4 (depends on 1)

The method of claim 1, wherein the third dielectric layer includes at least one of hafnium oxide, zirconium oxide, aluminum oxide or titanium oxide.

### Claim 5 (depends on 1)

The method of claim 1, wherein the fourth dielectric layer includes SiCN.

### Claim 6 (depends on 1)

The method of claim 1, wherein the trench is formed by plasma etching using a source gas including C4F6 and CHF3.

### Claim 7 (depends on 1)

The method of claim 1, wherein the fourth dielectric layer is formed by:
forming a blanket layer of the dielectric material for the fourth dielectric layer; and
performing an etching back operation using plasma etching.

### Claim 8 (depends on 7)

The method of claim 7, wherein a source gas of the plasma etching includes CH3F.

### Claim 9 (depends on 1)

The method of claim 1, wherein the sacrificial cladding layer is amorphous or polycrystalline Si or SiGe.

### Claim 10

A method of manufacturing a semiconductor device, comprising:
forming a fin structure;
forming an isolation insulating layer so that an upper portion of the fin structure is exposed from the isolation insulating layer;
forming a sacrificial layer over at least sidewalls of the exposed upper portion of the fin structure;
forming a first dielectric layer over the sacrificial layer;
forming a second dielectric layer made of a different material than the first dielectric layer over the first dielectric layer;
recessing the second dielectric layer;
forming a third dielectric layer made of a different material than the second dielectric layer over the recessed second dielectric layer;
partially removing the third dielectric layer to form a trench; and
forming a fourth dielectric layer by filling the trench with a dielectric material different from the third dielectric layer, thereby forming a wall fin structure.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
recessing a source/drain portion of the fin structure to form a recessed fin structure;
forming a source/drain epitaxial layer over the recessed fin structure;
forming a fifth dielectric layer over the source/drain epitaxial layer;
removing the fourth dielectric layer to form a space;
forming a contact opening in the fifth dielectric layer; and
forming a source/drain contact by filling the contact opening with one or more conductive materials.

### Claim 12 (depends on 11)

The method of claim 11, further comprising, after the fourth dielectric layer is removed, treating the space with plasma so that the third dielectric layer has a V-shape cross section.

### Claim 13 (depends on 12)

The method of claim 12, wherein a source gas of the plasma includes HBr.

### Claim 14 (depends on 12)

The method of claim 12, wherein a part of the source/drain contact is formed over the third dielectric layer having a V-shape cross section.

### Claim 15 (depends on 11)

The method of claim 11, further comprising:
removing the sacrificial layer to expose a channel region of the fin structure;
forming a gate dielectric layer over the channel region; and
forming a gate electrode over the gate dielectric layer.

### Claim 16 (depends on 11)

The method of claim 11, wherein:
the fin structure includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure, and
the method further comprises:
removing the sacrificial layer to expose a channel region of the fin structure;
removing the first semiconductor layers thereby releasing semiconductor wires or sheets formed of the second semiconductor layers;
forming a gate dielectric layer around the semiconductor wires or sheets; and
forming a gate electrode over the gate dielectric layer.

### Claim 17 (depends on 10)

The method of claim 10, wherein the third dielectric layer includes hafnium oxide and the fourth dielectric layer includes SiCN.

### Claim 18

A method of manufacturing a semiconductor device, comprising:
forming fin structures each including a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer;
forming an isolation insulating layer so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer;
forming a sacrificial cladding layer over at least sidewalls of the exposed hard mask layer and stacked layer;
forming a first dielectric layer over the sacrificial cladding layer, the first dielectric layer not fully filling a space between the fin structures;
forming a second dielectric layer made of a different material than the first dielectric layer over the first dielectric layer to fully fill the space between the fin structures;
recessing the second dielectric layer;
forming a third dielectric layer made of a different material than the second dielectric layer over the recessed second dielectric layer;
partially removing the third dielectric layer to form a trench;
forming a fourth dielectric layer by filling the trench with a dielectric material different from the third dielectric layer, thereby forming a wall fin structure;
removing the hard mask layer;
forming a sacrificial gate structure;
forming sidewall spacers on sidewalls of the sacrificial gate structure and sidewalls of a part of the wall fin structure;
forming a source/drain structure adjacent opposing sides of the sidewall spacers;
forming a fifth dielectric layer;
removing the sacrificial gate structure;
removing the sacrificial cladding layer;
removing the first semiconductor layers; and
forming a metal gate structure around the second semiconductor layers.

### Claim 19 (depends on 18)

The method of claim 18, wherein the third dielectric layer includes hafnium oxide and the fourth dielectric layer includes SiCN.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
removing the fourth dielectric layer to form a space;
forming a contact opening in the fifth dielectric layer; and
forming a source/drain contact by filling the contact opening with one or more conductive materials.