# US 12,002,836 B2 · Pixel with strained silicon layer for improving carrier mobility and blue response in imagers

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- Number: US 12,002,836 B2
- Document ID: US12002836B2
- Status: Granted
- Kind: B2
- Application number: 17/154,703
- Filed: 2021-01-21
- Published: 2021-08-05
- Granted: 2024-06-04
- Earliest claimed: 2003-07-07
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Chandra Mouli
- Web page: https://patentgrep.com/patent/US12002836B2

## CPC

- H10F 39/1825: {Multicolour image sensors having stacked structure, e.g. NPN, NPNPN or multiple quantum well [MQW] structures}
- H10F 39/014: {of CMOS image sensors}
- H10F 39/802: {Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes}
- H10F 39/803: {Pixels having integrated switching, control, storage or amplification elements}
- H10F 39/8033: {Photosensitive area}
- H10F 77/14: Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies
- H10F 30/24: the devices having only two potential barriers, e.g. bipolar phototransistors
- H10F 39/1847: {Multispectral infrared image sensors having a stacked structure, e.g. NPN, NPNPN or multiple quantum well [MQW] structures}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag, and improves blue response in imaging devices.

## Claims

### Claim 1

A system, comprising:
an imaging device including at least one pixel cell having a photosensor with a photosensitive region buried at least in part within a substrate such that the photosensitive region is separated from a strained silicon layer by an intermediary portion of the substrate;
a central processing unit operably connected to the imaging device via a first bus; and
a memory component operably connected to the central processing unit via a second bus, wherein:
the memory component is configured to (i) receive, via the first bus or the second bus, a digital image from the imaging device and (ii) store the digital image, and
the central processing unit is configured to (a) receive, via the second bus, the digital image from the memory component and (b) process the digital image.

### Claim 2 (depends on 1)

The system of claim 1, further comprising a memory controller, wherein:
the memory controller is operably connected to the imaging device via the first bus;
the memory controller is operably connected to the central processing unit via a third bus; and
the memory controller is operably connected to the memory component via the second bus.

### Claim 3 (depends on 2)

The system of claim 2, further comprising a primary bus bridge operably connecting the first bus to the second bus.

### Claim 4 (depends on 3)

The system of claim 3, wherein the memory controller and the primary bus bridge are integrated as a single device.

### Claim 5 (depends on 3)

The system of claim 3, further comprising an accelerated graphics port operably connected to the primary bus bridge.

### Claim 6 (depends on 1)

The system of claim 1, wherein the memory component is a memory card, a single inline memory module, or a dual inline memory module.

### Claim 7 (depends on 1)

The system of claim 1, wherein the memory component includes a serial presence detect memory.

### Claim 8 (depends on 1)

The system of claim 1, wherein:
the memory component is a first memory component;
the system further comprises a second memory component operably connected to the central processing unit via a third bus separate from the second bus; and
the second bus and the third bus are configured to be operated in parallel.

### Claim 9 (depends on 1)

The system of claim 1, wherein:
the memory component is a first memory component;
the system further comprises a second memory component operably connected to the central processing unit via a third bus separate from the second bus; and
the third bus is mapped to a different address range than the second bus.

### Claim 10 (depends on 1)

The system of claim 1, further comprising a multimedia processor operably connected to the imaging device via the first bus, wherein the multimedia processor is a sound card or a video capture card.

### Claim 11 (depends on 1)

The system of claim 1, further comprising a universal serial port controller configured to operably connect a universal serial bus device to the imaging device via the first bus.

### Claim 12 (depends on 1)

The system of claim 1, further comprising a storage controller operably connected to the imaging device via the first bus.

### Claim 13 (depends on 1)

The system of claim 1, wherein the system is an audio/video processor, an audio/video recorder, a gaming console, a digital television set, a wireless telephone, a wired telephone, a navigation device, a digital camera, or a digital recorder.

### Claim 14 (depends on 1)

The system of claim 1, wherein the imaging device, the central processing unit, or the memory component is an integrated circuit.

### Claim 15

A pixel cell, comprising a photosensor having a photosensitive region buried at least in part within a substrate such that the photosensitive region is separated from a strained silicon layer by an intermediary portion of the substrate.

### Claim 16 (depends on 15)

The pixel cell of claim 15, wherein the strained silicon layer is formed in an upper portion of the substrate.

### Claim 17 (depends on 1)

The pixel cell of claim 1, wherein the strained silicon layer includes a top silicon layer formed over a silicon-germanium layer.

### Claim 18 (depends on 15)

The pixel cell of claim 15, wherein the intermediary portion includes an undoped portion of the substrate.

### Claim 19 (depends on 15)

The pixel cell of claim 15, wherein the photosensitive region is buried entirely below the strained silicon layer.

### Claim 20

An imaging device comprising a plurality of pixel cells, wherein a pixel cell of the plurality of pixels cells includes a photosensitive region buried at least in part within a substrate such that the photosensitive region is separate from a strained silicon layer by an intermediary portion of the substrate.