# US 12,002,831 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,831 B2 - Document ID: US12002831B2 - Status: Granted - Kind: B2 - Application number: 17/266,838 - Filed: 2019-08-02 - Published: 2021-11-11 - Granted: 2024-06-04 - Earliest claimed: 2018-08-31 - Assignees: Sony Semiconductor Solutions Corporation - Applicants: Sony Semiconductor Solutions Corporation - Inventors: Hajime Yamagishi; Eiji Sato; Akira Yamazaki; Takayuki Sekihara; Makoto Hayafuchi; Syunsuke Ishizaki - Web page: https://patentgrep.com/patent/US12002831B2 ## CPC - H10F 39/809: {of hybrid image sensors} - H10F 39/018: {of hybrid image sensors} - H10F 39/199: {Back-illuminated image sensors} - H10F 39/8023: {Disposition of the elements in pixels, e.g. smaller elements in the centre of the imager compared to larger elements at the periphery} - H10F 39/811: {Interconnections} - H10W 80/00: Direct bonding of chips, wafers or substrates - H10W 90/00: Package configurations - H10F 39/8053: {Colour filters} - H10F 39/8057: {Optical shielding} - H10W 72/019: {of bond pads} - H10W 72/01935: {by plating, e.g. electroless plating or electroplating} - H10W 72/07236: {Soldering or alloying} - H10W 72/9232: {with additional elements interposed between layers} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 72/941: {Dispositions of bond pads} - H10W 72/944: {Dispositions of multiple bond pads} - H10W 72/963: {Providing mechanical bonding or support, e.g. dummy bond pads} - H10W 72/967: {Multiple bond pads having different functions} - H10W 80/016: {Cleaning} - H10W 80/312: {characterised by the direct bonding of electrically conductive pads} - H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers} - H10W 80/701: {characterised by the pads after the direct bonding} - H10W 80/732: {having shape changed during the connecting} - H10W 80/743: {having disposition changed during the connecting} - H10W 90/792: {between multiple chips} - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Effective use is achieved of a region in a proximity of a joining plane of semiconductor substrates in a semiconductor device including a stacked semiconductor substrate in which multilayer wiring layers of a plurality of semiconductor substrates are electrically connected to each other. The stacked semiconductor substrate includes plural semiconductor substrates on each of which a multilayer wiring layer is formed. In this stacked semiconductor substrate, the multilayer wiring layers are joined together and electrically connected to each other. In the proximity of a joining plane of the plurality of semiconductor substrates, a conductor is formed. This conductor is formed such that it is electrified in a direction of the joining plane. ## Claims ### Claim 1 A semiconductor device, comprising: a first semiconductor substrate including a first multilayer wiring layer; and a second semiconductor substrate including a second multilayer wiring layer, wherein the first semiconductor substrate and the second semiconductor substrate are joined together with the first multilayer wiring layer and the second multilayer wiring layer directly connected to each other to form a plurality of conductors in a proximity of a joining plane of the of the first and second semiconductor substrates, wherein connection holes are formed in either or both of the first multilayer wiring layer and the second multilayer wiring layer, wherein rivets are fitted to the connection holes, and wherein the plurality of conductors are electrified in a direction of the joining plane. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein at least some of the plurality of conductors formed in the proximity of the joining plane have a plane long side equal to or greater than twice a width of a connection hole connection face. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein only one of the first multilayer wiring layer and the second multilayer wiring layer has the connection holes. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein at least some of the plurality of conductors formed in the proximity of the joining plane on a side of the first semiconductor substrate are not electrically connected to an opposing conductor on a side of the second semiconductor substrate. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein at least some of the plurality of conductors formed in the proximity of the joining plane are different in shape from an opposing conductor. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein at least some of the plurality of conductors formed in the proximity of the joining plane are arranged in a displaced relation to an opposing conductor by a predetermined direction in a direction of the joining plane. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein at least some of the plurality of conductors formed in the proximity of the joining plane have a shape having a plane aspect ratio higher than one. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein at least some of the plurality of conductors formed in the proximity of the joining plane are joined to an opposed conductor on the joining plane so as to cross with each other in a longitudinal direction on the joining plane. ### Claim 9 (depends on 7) The semiconductor device according to claim 7, wherein at least some of the plurality of conductors formed in the proximity of the joining plane are joined to an opposed conductor on the joining plane so as to extend in parallel in a longitudinal direction on the joining plane. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein at least some of the plurality of conductors formed in the proximity of the joining plane have a rectangular shape or an elliptical shape having a plane aspect ratio higher than one. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein at least some of the plurality of conductors formed in the proximity of the joining plane has a polygonal shape configured from a combination of rectangles having a plane aspect ratio higher than one. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, wherein at least some of the plurality of conductors formed in the proximity of the joining plane are provided in a region that surrounds an inner side circumference of an input/output pad. ### Claim 13 (depends on 1) The semiconductor device according to claim 1, wherein at least some of the plurality of conductors formed in the proximity of the joining plane are provided in a rectangular region on an inner side of an input/output pad. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, wherein at least some of the plurality of conductors formed in the proximity of the joining plane are provided in parallel to a power supply wiring.