# US 12,002,814 B2 · Array substrate and manufacturing method thereof

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- Number: US 12,002,814 B2
- Document ID: US12002814B2
- Status: Granted
- Kind: B2
- Application number: 17/057,629
- Filed: 2020-10-20
- Published: 2022-09-29
- Granted: 2024-06-04
- Earliest claimed: 2020-09-04
- Assignees: Tcl China Star Optoelectronics Technology Co., Ltd.
- Applicants: Tcl China Star Optoelectronics Technology Co., Ltd.
- Inventors: Xu Huang
- Web page: https://patentgrep.com/patent/US12002814B2

## CPC

- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present application provides an array substrate and a manufacturing method thereof. The array substrate includes a substrate; an active layer comprising a channel region; a gate insulating layer; a gate corresponding to the channel region of the active layer; and a source and a drain disposed at opposite ends of the active layer, wherein the gate has a groove structure, the groove structure has an opening facing the active layer, and a region of the groove structure corresponding to the active layer is the channel region.

## Claims

### Claim 1

An array substrate, comprising:
a substrate;
an active layer comprising a channel region;
a gate insulating layer;
a gate corresponding to the channel region of the active layer; and
a source and a drain disposed at opposite ends of the active layer,
wherein the gate has a groove structure, the groove structure has an opening facing the active layer, and a region of the groove structure corresponding to the active layer is the channel region,
wherein the array substrate further comprises a buffer layer, the gate comprises a first gate and a second gate, and the gate insulating layer comprises a first gate insulating layer and a second gate insulating layer;
wherein the substrate, the buffer layer, the first gate, the first gate insulating layer, the active layer, the second gate insulating layer, and the second gate are stacked in sequence; and
wherein the buffer layer is disposed corresponding to the channel region of the active layer, the first gate has a groove structure covering opposite side surfaces and an upper surface of the buffer layer, the first gate insulating layer has a groove structure covering opposite side surfaces and an upper surface of the first gate, the active layer has a groove structure covering opposite side surfaces and an upper surface of the first gate insulating layer, the second gate insulating layer has a groove structure covering opposite side surfaces and an upper surface of the active layer, and the second gate covers opposite side surfaces and an upper surface of the second gate insulating layer.

### Claim 2 (depends on 1)

The array substrate according to claim 1, wherein the active layer, the gate insulating layer, and the gate are stacked in sequence; the gate insulating layer has a groove structure covering opposite side surfaces and an upper surface of the active layer corresponding to the channel region; and the gate covers opposite side surfaces and an upper surface of the gate insulating layer.

### Claim 3 (depends on 2)

The array substrate according to claim 2, wherein the channel region of the active layer comprises a first channel region defined on the upper surface of the active layer, and a second channel region and a third channel region defined on the opposite side surfaces of the active layer, respectively, and the second channel region, the first channel region, and the third channel region are continuous; and
wherein the gate comprises a top portion corresponding to the first channel region, a first side portion corresponding to the second channel region, and a second side portion corresponding to the third channel region, and the top portion, the first side portion, and the second side portion of the gate together constitute the groove structure.

### Claim 4 (depends on 3)

The array substrate according to claim 3, wherein the groove structure of the gate extends in a first direction, and a second direction is perpendicular to the first direction; and wherein the gate, the gate insulating layer, and the active layer constitute a three-dimensional channel structure, and a width of the three-dimensional channel structure is a sum of side lengths of cross sections of the top portion, the first side portion, and the second side portion of the gate in the second direction.

### Claim 5 (depends on 1)

The array substrate according to claim 1, wherein the gate electrode, the gate insulating layer, and the active layer are stacked in sequence; the gate insulating layer has a groove structure, and the gate insulating layer covers opposite side surfaces and a lower surface of the active layer corresponding channel region, and the gate covers opposite side surfaces and a lower surface of the gate insulating layer.

### Claim 6 (depends on 5)

The array substrate according to claim 5, wherein the channel region of the active layer comprises a first channel region defined on an upper surface of the active layer, a second channel region and a third channel region defined on opposite side surfaces of the active layer, respectively, and the second channel region, the first channel region, and the third channel region are continuous; and
wherein the gate comprises a top portion corresponding to the first channel region, a first side portion corresponding to the second channel region, and a second side portion corresponding to the third channel region, and the top portion, the first side portion, and the second side portion of the gate portion together constitute the groove structure.

### Claim 7 (depends on 6)

The array substrate according to claim 6, wherein the groove structure of the gate extends in a first direction, and a second direction is perpendicular to the first direction; and wherein the gate, the gate insulating layer, and the active layer constitute a three-dimensional channel structure, and a width of the three-dimensional channel structure is a sum of side lengths of cross sections of the top portion, the first side portion, and the second side portion of the gate in the second direction.

### Claim 8 (depends on 1)

The array substrate according to claim 1, wherein the channel region of the active layer comprises a first channel region defined on the upper surface of the active layer, and a second channel region and a third channel region defined on opposite side surfaces of the active layer, respectively, and the second channel region, the first channel region, and the third channel region are continuous;
wherein the first gate comprises a top portion corresponding to the first channel region, a first side portion corresponding to the second channel region, and a second side portion corresponding to the third channel region, and the top portion, the first side portion, and the second side portion of the first gate together constitute the groove structure; and
wherein the second gate comprises a top portion corresponding to the first channel region, a third side portion corresponding to the second channel region, and a fourth side portion corresponding to the third channel region, and the top portion, the third side portion, and the fourth side portion of the second gate together constitute the groove structure.

### Claim 9 (depends on 8)

The array substrate according to claim 8, wherein the groove structure of the first gate extends in a first direction, and a second direction is perpendicular to the first direction;
wherein the buffer layer, the first gate, the first gate insulating layer, the active layer, the second gate insulating layer, and the second gate constitute a three-dimensional channel structure; and
wherein a width of the three-dimensional channel structure is a sum of side lengths of cross sections of the top portion, the first side portion, and the second side portion of the first gate in the second direction and side lengths of cross sections of the top portion, the third side portion, and the fourth side portion of the second gate in the second direction.

### Claim 10

A method of manufacturing an array substrate, comprising the following steps:
step S10: forming a first metal layer on a buffer layer, and patterning the first metal layer to form a first gate;
step S20: forming a first gate insulating layer on the first gate;
step S30: forming an active layer on the first gate insulating layer, wherein the active layer comprises a channel region, a source contact region, and a drain contact region, and a drain contact region, and the source contact region and the drain contact region are spaced apart from each other by the channel region;
step S40: forming a second gate insulating layer on the active layer;
step S50: forming a second metal layer on the second gate insulating layer, and patterning the second metal layer to form a second gate corresponding to the channel region, a source in contact with the source contact region, and a drain in contact with the drain contact region;
step S60: sequentially forming a passivation layer and a planarization layer on the second gate, the source, and the drain; and
step S70: forming an electrode layer on the planarization layer.

### Claim 11 (depends on 10)

The method of manufacturing the array substrate according to claim 10, wherein the buffer layer is disposed corresponding to the channel region of the active layer, the first gate has a groove structure covering opposite side surfaces and an upper surface of the buffer layer, the first gate insulating layer has a groove structure covering opposite side surfaces and an upper surface of the first gate, the active layer has a groove structure covering opposite side surfaces and an upper surface of the first gate insulating layer, the second gate insulating layer has a groove structure covering opposite side surfaces and an upper surface of the active layer, and the second gate covers opposite side surfaces and an upper surface of the second gate insulating layer.

### Claim 12 (depends on 11)

The method of manufacturing the array substrate according to claim 11, wherein the channel region of the active layer comprises a first channel region defined on the upper surface of the active layer, and a second channel region and a third channel region defined on opposite side surfaces of the active layer, respectively, and the second channel region, the first channel region, and the third channel region are continuous;
wherein the first gate comprises a top portion corresponding to the first channel region, a first side portion corresponding to the second channel region, and a second side portion corresponding to the third channel region, and the top portion, the first side portion, and the second side portion of the first gate together constitute the groove structure; and
wherein the second gate comprises a top portion corresponding to the first channel region, a third side portion corresponding to the second channel region, and a fourth side portion corresponding to the third channel region, and the top portion, the third side portion, and the fourth side portion of the second gate together constitute the groove structure.

### Claim 13 (depends on 12)

The method of manufacturing the array substrate according to claim 12, wherein the groove structure of the first gate is a first direction, and a second direction is perpendicular to the first direction;
wherein the buffer layer, the first gate, the first gate insulating layer, the active layer, the second gate insulating layer, and the second gate constitute a three-dimensional channel structure; and
wherein a width of the three-dimensional channel structure is a sum of side lengths of cross sections of the top portion, the first side portion, and the second side portion of the first gate in the second direction and side lengths of cross sections of the top portion, the third side portion, and the fourth side portion of the second gate in the second direction.

### Claim 14 (depends on 13)

The method of manufacturing the array substrate according to claim 13, wherein a cross section of the three-dimensional channel structure perpendicular to an extending direction of the groove structure of the first gate has a trapezoid shape, a square shape, and/or a fin shape.