# US 12,002,813 B2 · Method for forming semiconductor-on-insulator (SOI) substrate by cleaving a multilayer structure along voids to separate a substrate

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- Number: US 12,002,813 B2
- Document ID: US12002813B2
- Status: Granted
- Kind: B2
- Application number: 17/461,370
- Filed: 2021-08-30
- Published: 2023-03-02
- Granted: 2024-06-04
- Earliest claimed: 2021-08-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Yu-Hung Cheng; Ching I Li; Chia-Shiung Tsai
- Web page: https://patentgrep.com/patent/US12002813B2

## CPC

- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10P 90/00: Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P 50/642: {Chemical etching}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 90/1906: {Preparing SOI wafers}
- H10P 90/1924: {with separation/delamination along a porous layer}
- H10P 95/06: {Planarisation of inorganic insulating materials}
- H10W 10/021: {of air gaps}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 10/20: Air gaps
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming an SOI substrate is provided. The method includes following operations. A recycle substrate is received. A first multilayered structure is formed on the recycle substrate. A trench is formed in the first multilayered structure. A lateral etching is performed to remove portions of sidewalls of the trench to form a recess in the first multilayered structure. The trench and the recess are sealed with an epitaxial layer, and a potential cracking interface is formed in the first multilayered structure. A second multilayered structure is formed over the first multilayered structure. The device layer of the recycle substrate is bonded to an insulator layer over an carrier substrate. The first multilayered structure is cleaved along the potential cracking interface to separate the recycle substrate from the second multilayered structure, the insulator layer and the carrier substrate. The device layer is exposed.

## Claims

### Claim 1

A method for forming a semiconductor-on-insulator (SOI) substrate, comprising:
receiving a first substrate;
forming a first multilayered structure over the first substrate, wherein the first multilayered structure comprises a first etch stop layer, a first semiconductor layer over the first etch stop layer, a second semiconductor layer over the first semiconductor layer, and a sacrificial layer between the first semiconductor layer and the second semiconductor layer;
forming a plurality of trenches in the first multilayered structure, wherein the first semiconductor layer, the second semiconductor layer and the sacrificial layer are exposed through sidewalls of the trenches;
performing a lateral etching to remove portions of the sacrificial layer,
performing an epitaxial growth operation to seal the trenches with a first semiconductor material and form a plurality of voids in the first multilayered structure;
forming a second multilayered structure over the first substrate, wherein the second multilayered structure comprises a second etch stop layer and a device layer over the second etch stop layer;
receiving a second substrate, wherein an insulator layer is formed over the second substrate;
bonding the device layer over the first substrate to the insulator layer over the second substrate;
cleaving the first multilayered structure along the voids to separate the first substrate, the first etch stop layer, the first semiconductor layer, and a first portion of the sacrificial layer from a second portion of the sacrificial layer, the second semiconductor layer, the second multilayered structure, the insulator layer and the second substrate; and
removing the second semiconductor layer, the second portion of the sacrificial layer and the second etch stop layer to expose the device layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first semiconductor layer, the second semiconductor layer and the device layer comprise the first semiconductor material.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first etch stop layer, the sacrificial layer and the second etch stop layer comprise the first semiconductor material and a second semiconductor material, and the second semiconductor material is different from the first semiconductor material.

### Claim 4 (depends on 3)

The method of claim 3, wherein the first etch stop layer and the second etch stop layer further comprises dopants.

### Claim 5 (depends on 1)

The method of claim 1, wherein a thickness of the first semiconductor layer and a thickness of the second semiconductor layer are greater than a thickness of the etch stop layer and a thickness of the sacrificial layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the removing of the second semiconductor layer, the second portion of the sacrificial layer and the second etch stop layer further comprises:
removing the second semiconductor layer and the second portion of the sacrificial layer to expose the second etch stop layer by a wet etching; and
removing the second etch stop layer to expose the device layer.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
removing the first portion of the sacrificial layer and the first semiconductor layer to expose the first etch stop layer by a wet etching; and
removing the first etch stop layer to expose the first substrate.

### Claim 8

A method for forming an SOI substrate, comprising:
receiving a recycle substrate, wherein a first multilayered structure is formed over the recycle substrate;
forming a trench in the first multilayered structure;
performing a lateral etching to remove portions of sidewalls of the trench to form a recess in the first multilayered structure;
sealing the trench and the recess with an epitaxial layer to form a potential cracking interface in the first multilayered structure;
forming a second multilayered structure over the first multilayered structure, wherein the second multilayered structure comprises at least a device layer;
receiving a carrier substrate, wherein an insulator layer is formed over the carrier substrate;
bonding the device layer over the recycle substrate to the insulator layer over the carrier substrate;
cleaving the first multilayered structure along the potential cracking interface to separate the recycle substrate from the second multilayered structure, the insulator layer and the carrier substrate; and
exposing the device layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein the first multilayered structure comprises a first etch stop layer over the recycle substrate, a first semiconductor layer over the first etch stop layer, a sacrificial layer over the first semiconductor layer, and a second semiconductor layer over the sacrificial layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein the forming of the trench in the first multilayered structure comprises:
forming a patterned mask layer over the first multilayered structure; and
removing a portion of the second semiconductor layer, a portion of the sacrificial layer and a portion of the first semiconductor layer to form the trench through the patterned mask layer,
wherein a bottom of the trench is separated from the first etch stop layer by the first semiconductor layer.

### Claim 11 (depends on 9)

The method of claim 9, wherein the performing of the lateral etching comprises laterally removing a portion of the sacrificial layer to form the recess laterally extending in the sacrificial layer.

### Claim 12 (depends on 8)

The method of claim 8, wherein the second multilayered structure further comprises a second etch stop layer, and the second etch stop layer is between the device layer and the epitaxial layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein the exposing of the device layer further comprises:
performing a wet etching to remove the first multilayered structure and the epitaxial layer to expose the second etch stop layer; and
removing the second etch stop layer to expose the device layer.

### Claim 14 (depends on 8)

The method of claim 8, further comprising performing an anneal to smooth a surface of the device layer.

### Claim 15

A method for forming an SOI substrate, comprising:
receiving a substrate;
sequentially forming a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer over the substrate;
removing portions of the second semiconductor layer, the third semiconductor layer and the fourth semiconductor layer to form a plurality of mesas separated from each other by a plurality of trenches over the substrate;
performing a lateral etching to remove a portion of the third semiconductor layer to form an island between the second semiconductor layer and the fourth semiconductor layer within each mesa; and
performing an epitaxial growth operation to seal the trench with a semiconductor material and form a first void extending along a first direction and a second void extending along a second direction different from the first direction.

### Claim 16 (depends on 15)

The method of claim 15, wherein the first direction is perpendicular to a surface of the first substrate, and the second direction is parallel to the surface of the first substrate.

### Claim 17 (depends on 15)

The method of claim 15, wherein the semiconductor material forms sidewalls, a bottom and a top of the first void.

### Claim 18 (depends on 15)

The method of claim 15, wherein the semiconductor material and the third semiconductor layer form sidewalls of the second void, the second semiconductor layer forms a bottom of the second void, and the semiconductor material forms a top of the second void.

### Claim 19 (depends on 15)

The method of claim 15, further comprising:
forming an etch stop layer over the substrate after the sealing of the trench; and
forming a device layer over the etch stop layer.

### Claim 20 (depends on 19)

The method of claim 19, further comprising bonding the device layer to an insulator layer over a second substrate.