# US 12,002,811 B2 · Semiconductor device and manufacturing method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,002,811 B2
- Document ID: US12002811B2
- Status: Granted
- Kind: B2
- Application number: 18/132,862
- Filed: 2023-04-10
- Published: 2023-08-10
- Granted: 2024-06-04
- Earliest claimed: 2015-11-05
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ka-Hing Fung
- Web page: https://patentgrep.com/patent/US12002811B2

## CPC

- H10D 84/853: {comprising FinFETs}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a first channel region disposed over a substrate, a first source region and a first drain region disposed over the substrate and connected to the first channel region such that the first channel region is disposed between the first source region and the first drain region, a gate dielectric layer disposed on and wrapping the first channel region, a gate electrode layer disposed on the gate dielectric layer and wrapping the first channel region, and a second source region and a second drain region disposed over the substrate and below the first source region and the first drain region, respectively. The second source region and the second drain region are in contact with the gate dielectric layer. A lattice constant of the first source region and the first drain region is different from a lattice constant of the second source region and the second drain region.

## Claims

### Claim 1

A semiconductor device including a gate-all-around field effect transistor (GAA FET), the GAA FET comprising:
first channel regions disposed and vertically arranged over a bottom fin structure protruding from a substrate;
a source epitaxial layer disposed over and in contact with the bottom fin structure and connected to the first channel regions;
a gate dielectric layer wrapping around the first channel region;
a gate electrode layer disposed on the gate dielectric layer; and
sidewall spacers disposed along sidewalls of the first channel regions;
wherein a top of the source epitaxial layer is higher than a top of the sidewall spacers.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein:
part of the gate dielectric layer and the gate electrode is disposed between a bottommost one of the first channel regions and the bottom fin structure.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein:
the first channel regions are made of Si or a Si-based compound, and
the source epitaxial layer is made of Si1-xGex, where x is between 0.4 to 0.7.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein:
the GAA-FET further comprises an interlayer dielectric (ILD) layer covering the first channel regions and the source epitaxial layer, and
the ILD layer is in contact with the source epitaxial layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the GAA-FET is an n-type FET.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein each of the first channel regions have a thickness in a range from 5 nm to 30 nm.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the sidewall spacers are made of SiON, SiOCN or SiCN.

### Claim 8

A semiconductor device, comprising a p-channel gate-all-around field effect transistor (p-GAA FET) and an n-channel gate-all-around around field effect transistor (n-GAA FET), wherein:
each of the p-GAA FET and the n-GAA-FET comprises:
a bottom fin structure disposed over a substrate;
a first channel region disposed over the substrate; and
a source/drain (S/D) structure formed over the bottom fin structure, and in the p-GAA FET:
the S/D structure includes a first S/D layer and a second S/D layer having a different lattice constant from the first S/D layer,
the first S/D layer is connected to the first channel region,
the first S/D layer is made of a different material than the first channel region, and
the second S/D layer is completely surrounded by the first S/D layer.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein:
the first channel regions are made of Si or a Si-based compound, and
the first S/D layer is made of Ge or SiGe.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein:
the second S/D layer are made of SiGe, and
a Ge content of the first S/D layer is greater than a Ge content of the second S/D layer.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein multiple first channel regions and corresponding multiple first S/D layers are provided in a vertical direction.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein:
each of the p-GAA FET and the n-GAA-FET comprises a gate structure wrapping around the first channel region,
in the n-GAA-FET:
the S/D structure includes a third S/D layer,
the third S/D layer is connected to the first channel region and in contact with the gate structure, and
the third S/D layer has a different lattice constant than the first channel region.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein, in the n-GAA-FET, the S/D structure includes no layered structure.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, wherein:
each of the p-GAA FET and the n-GAA-FET comprises a bottom fin structure disposed over the substrate, and
in the n-GAA-FET, the third S/D layer is in contact with the bottom fin structure.

### Claim 15 (depends on 8)

The semiconductor device of claim 8, wherein, in the p-GAA-FET, the first S/D layer is separated from the bottom fin structure.

### Claim 16

A semiconductor device including a gate-all-around field effect transistor (GAA FET), the GAA FET, comprising:
a first channel region disposed over a substrate;
a second channel region disposed over the substrate at a different height than the first channel region;
a gate structure wrapping around the first channel region and the second channel region;
a first source region disposed over the substrate and connected to the first channel region and the second channel region; and
a second source region disposed over the substrate, wherein:
a lattice constant of the first source region is different from a lattice constant of the second source region, and
the first source region completely surrounds the second source region.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein:
the first channel region is made of Si or a Si-based compound, and
the first source region is made of Ge or SiGe.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein:
the second source region is made of SiGe, and
a Ge content of the second source region is smaller than a Ge content of the first source region.

### Claim 19 (depends on 16)

The semiconductor device of claim 16, further comprising a third source region disposed between the substrate and the first source region, and made of a same material as the second source region.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein:
the GAA-FET further comprises an interlayer dielectric (ILD) layer covering the first channel region, and
an insulating layer made of a different material than the ILD layer is disposed in contact with the third source region.