# US 12,002,810 B2 · Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach

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- Number: US 12,002,810 B2
- Document ID: US12002810B2
- Status: Granted
- Kind: B2
- Application number: 16/146,800
- Filed: 2018-09-28
- Published: 2020-04-02
- Granted: 2024-06-04
- Earliest claimed: 2018-09-28
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Dax M. Crum; Biswajeet Guha; Leonard Guler; Tahir Ghani
- Web page: https://patentgrep.com/patent/US12002810B2

## CPC

- H10D 84/853: {comprising FinFETs}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 84/0128: {Manufacturing their channels}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up approach, are described. For example, integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. The first vertical arrangement of nanowires has a greater number of nanowires than the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has an uppermost nanowire co-planar with an uppermost nanowire of the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has a bottommost nanowire below a bottommost nanowire of the second vertical arrangement of nanowires. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires.

## Claims

### Claim 1

An integrated circuit structure, comprising:
a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of nanowires than the second vertical arrangement of nanowires, the first vertical arrangement of nanowires having an uppermost nanowire co-planar with an uppermost nanowire of the second vertical arrangement of nanowires, and the first vertical arrangement of nanowires having a bottommost nanowire below a bottommost nanowire of the second vertical arrangement of nanowires, wherein the first vertical arrangement of nanowires is over a first fin, the first fin having an uppermost surface, and the second vertical arrangement of nanowires is over a second fin, the second fin having an uppermost surface below the uppermost surface of the first fin, wherein the bottommost nanowire of the first vertical arrangement of nanowires is vertically spaced apart from the first fin by a first distance, and wherein the bottommost nanowire of the second vertical arrangement of nanowires is vertically spaced apart from the second fin by a second distance, the second distance greater than the first distance;
a first gate stack over the first vertical arrangement of nanowires; and
a second gate stack over the second vertical arrangement of nanowires.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the nanowires of the first vertical arrangement of nanowires have a horizontal width the same as a horizontal width of the nanowires of the second vertical arrangement of nanowires.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein the nanowires of the first vertical arrangement of nanowires have a horizontal width greater than a horizontal width of the nanowires of the second vertical arrangement of nanowires.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, wherein the nanowires of the first vertical arrangement of nanowires have a horizontal width less than a horizontal width of the nanowires of the second vertical arrangement of nanowires.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, further comprising:
first epitaxial source or drain structures at ends of the first vertical arrangement of nanowires; and
second epitaxial source or drain structures at ends of the second vertical arrangement of nanowires.

### Claim 6 (depends on 5)

The integrated circuit structure of claim 5, wherein the first and second epitaxial source or drain structures are discrete first and second epitaxial source or drain structures.

### Claim 7 (depends on 5)

The integrated circuit structure of claim 5, wherein the first and second epitaxial source or drain structures are non-discrete first and second epitaxial source or drain structures.

### Claim 8 (depends on 5)

The integrated circuit structure of claim 5, wherein the first gate stack has dielectric sidewall spacers, and the first epitaxial source or drain structures are first embedded epitaxial source or drain structures extending beneath the dielectric sidewalls spacers of the first gate stack, and wherein the second gate stack has dielectric sidewall spacers, and the second epitaxial source or drain structures are second embedded epitaxial source or drain structures extending beneath the dielectric sidewalls spacers of the second gate stack.

### Claim 9 (depends on 5)

The integrated circuit of claim 5, further comprising:
a first pair of conductive contact structures coupled to the first epitaxial source or drain structures; and
a second pair of conductive contact structures coupled to the second epitaxial source or drain structures.

### Claim 10 (depends on 9)

The integrated circuit structure of claim 9, wherein at least one of the first and second pairs of conductive contact structures is an asymmetric pair of conductive contact structures.

### Claim 11 (depends on 1)

The integrated circuit structure of claim 1, wherein the first fin has an upper surface above an upper surface of the second fin.

### Claim 12 (depends on 1)

The integrated circuit of claim 1, further comprising:
a gate endcap isolation structure between and in contact with the first gate stack and the second gate stack.

### Claim 13 (depends on 1)

The integrated circuit structure of claim 1, wherein the first and second gate stacks each comprise a high-k gate dielectric layer and a metal gate electrode.