# US 12,002,809 B2 · Method to enhance 3D horizontal nanosheets device performance

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- Number: US 12,002,809 B2
- Document ID: US12002809B2
- Status: Granted
- Kind: B2
- Application number: 17/469,939
- Filed: 2021-09-09
- Published: 2022-07-28
- Granted: 2024-06-04
- Earliest claimed: 2021-01-26
- Assignees: Tokyo Electron Limited
- Applicants: Tokyo Electron Limited
- Inventors: Mark I. Gardner; H. Jim Fulford
- Web page: https://patentgrep.com/patent/US12002809B2

## CPC

- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10D 62/121: {oriented parallel to substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Aspects of the present disclosure provide a method of fabricating a semiconductor device including a plurality of vertically stacked transistors. For example, the method can include providing a vertical stack of alternating horizontal first and second layers, the second layers forming channels of the transistors. The method can further include uncovering the second layers. The method can further include forming a first shell on a first one of the uncovered second layers, the first shell and the first one of the uncovered second layers forming a first channel structure of a first one of the transistors.

## Claims

### Claim 1

A method of fabricating a semiconductor device including a plurality of vertically stacked transistors, comprising:
providing a vertical stack of alternating horizontal first and second layers, the second layers forming channels of the transistors;
uncovering the second layers;
forming a first shell on a first one of the uncovered second layers, the first shell and the first one of the uncovered second layers forming a first channel structure of a first one of the transistors; and
forming a second shell on a second one of the uncovered second layers, the second shell and the second one of the uncovered second layers forming a second channel structure of a second one of the transistors, wherein the first channel structure is a P-type channel structure, and the second channel structure is an N-type channel structure, or
forming a second shell on a second one of the uncovered second layers, the second shell and the second one of the uncovered second layers forming a portion of a second channel structure of a second one of the transistors, wherein the first and second shells include different materials.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming a first shell on a first one of the uncovered second layers includes epitaxially growing a first shell on a first one of the uncovered second layers.

### Claim 3 (depends on 2)

The method of claim 2, wherein at least one of the first shell and the second layers includes an element selected from groups III, IV and V of the periodic table.

### Claim 4 (depends on 3)

The method of claim 3, wherein at least one of the first shell and the second layers includes boron (B), carbon (C), nitrogen (N), aluminum (Al), silicon (Si), phosphorus (P), gallium (Ga), germanium (Ge), arsenic (As), indium (In), tin (Sn), antimony (Sb), or a combination thereof.

### Claim 5 (depends on 1)

The method of claim 1, comprising:
forming the second shell on the second one of the uncovered second layers, the second shell and the second one of the uncovered second layers forming the second channel structure of the second one of the transistors,
wherein the first channel structure is the P-type channel structure, and the second channel structure is the N-type channel structure.

### Claim 6 (depends on 1)

The method of claim 1, comprising:
forming the second shell on the second one of the uncovered second layers, the second shell and the second one of the uncovered second layers forming the portion of the second channel structure of the second one of the transistors,
wherein the first and second shells include different materials.

### Claim 7 (depends on 1)

The method of claim 1, wherein providing a vertical stack of alternating horizontal first and second layers includes epitaxially growing alternating horizontal first and second layers.

### Claim 8

A method of fabricating a semiconductor device including a plurality of vertically stacked transistors, comprising:
providing a vertical stack of alternating horizontal first and second layers, the second layers forming channels of the transistors;
uncovering the second layers; and
forming a first shell on a first one of the uncovered second layers, the first shell and the first one of the uncovered second layers forming a first channel structure of a first one of the transistors,
wherein providing a vertical stack of alternating horizontal first and second layers includes bonding two sub-stacks of alternating horizontal first and second layers.

### Claim 9 (depends on 1)

The method of claim 1, wherein uncovering the second layers includes:
removing an end portion of the first layers in a channel direction to form indents;
forming spacers to fill the indents; and
removing a remainder of the first layers.

### Claim 10 (depends on 1)

The method of claim 1, wherein forming a first shell on a first one of the uncovered second layers includes forming a first shell around a first one of the uncovered second layers.

### Claim 11 (depends on 1)

The method of claim 1, further comprising forming a gate electrode around the first shell and a remainder of the second layers.

### Claim 12 (depends on 1)

The method of claim 1, further comprising, prior to forming a first shell on a first one of the uncovered second layers, thinning a first one of the uncovered second layers,
wherein forming a first shell on a first one of the uncovered second layers includes forming a first shell on the thinned first one of the uncover second layers.

### Claim 13

A semiconductor device, comprising:
a vertical stack of horizontal channels of a plurality of transistors;
a first shell formed on a first one of the channels, the first shell and the first one of the channels forming a first channel structure of a first one of the transistors; and
a second shell formed on a second one of the channels, the second shell and the second one of the channels forming a second channel structure of a second one of the transistors, wherein the first channel structure is a P-type channel structure, and the second channel structure is an N-type channel structure, or
a second shell formed on a second one of the channels, the second shell and the second one of the channels forming a second channel structure of a second one of the transistors, wherein the first and second shells include different materials.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the first shell includes an epitaxy material.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein at least one of the first shell and the channels includes an element selected from groups III, IV and V of the periodic table.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein at least one of the first shell and the channels includes B, C, N, Al, Si, P, Ga, Ge, As, In, Sn, Sb, or a combination thereof.

### Claim 17 (depends on 13)

The semiconductor device of claim 13, comprising:
the second shell formed on the second one of the channels, the second shell and the second one of the channels forming the second channel structure of the second one of the transistors,
wherein the first channel structure is the P-type channel structure, and the second channel structure is the N-type channel structure.

### Claim 18 (depends on 13)

The semiconductor device of claim 13, comprising:
the second shell formed on the second one of the channels, the second shell and the second one of the channels forming the second channel structure of the second one of the transistors,
wherein the first and second shells include different materials.

### Claim 19 (depends on 13)

The semiconductor device of claim 13, wherein the first shell is formed around the first one of the channels.

### Claim 20 (depends on 13)

The semiconductor device of claim 13, comprising:
a gate electrode formed around the first shell and a remainder of the channels.