# US 12,002,808 B2 · Dual dielectric pillar fork sheet device

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- Number: US 12,002,808 B2
- Document ID: US12002808B2
- Status: Granted
- Kind: B2
- Application number: 17/397,242
- Filed: 2021-08-09
- Published: 2023-02-09
- Granted: 2024-06-04
- Earliest claimed: 2021-08-09
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Ruilong Xie; Julien Frougier; Kangguo Cheng; Dimitri Houssameddine
- Web page: https://patentgrep.com/patent/US12002808B2

## CPC

- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/852: {comprising forksheet IGFETs}
- H10P 14/3452: {Microstructure}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A forksheet transistor device includes a dual dielectric pillar that includes a first dielectric and a second dielectric that is different from the first dielectric. The dual dielectric pillar physically separates pFET elements from nFET elements. For example, the first dielectric physically separates a pFET gate from a nFET gate while the second dielectric physically separates a pFET source/drain region from a nFET source drain region. When it is advantageous to electrically connect the pFET gate and the nFET gate, the first dielectric may be etched selective to the second dielectric to form a gate connector trench within the dual dielectric pillar. Subsequently, an electrically conductive gate connector strap may be formed within the gate connector trench to electrically connect the pFET gate and the nFET gate.

## Claims

### Claim 1

A forksheet nanosheet semiconductor device fabrication method comprising:
forming a plurality of channel nanosheet layers upon a substrate;
forming a dielectric pillar comprising a first dielectric within the, plurality of channel nanosheet layers thereby forming a first nanosheet stack directly against a first sidewall of the dielectric pillar and a second nanosheet stack directly against a second sidewall of the dielectric pillar;
forming a pair of sacrificial gate structures around the first nanosheet stack and around the second nanosheet stack;
forming a trench within the dielectric pillar self-aligned to and between the pair of sacrificial gate structures; and
forming a second dielectric different than the first dielectric within the trench to form a dual dielectric pillar.

### Claim 2 (depends on 1)

The fabrication method of claim 1, further comprising:
partially removing at least a portion of the second dielectric selective to the first dielectric to form a pair of connector trenches with each gate connector trench of the pair of connector trenches exposing a portion of a pair of replacement gate structures that are formed in place of and after a removal of the pair of sacrificial gate structures.

### Claim 3 (depends on 2)

The fabrication method of claim 2, further comprising:
forming a conductive material within the pair of gate connector trenches.

### Claim 4 (depends on 2)

The fabrication method of claim 2, wherein a bottom surface of the trench is above a top surface of the substrate.

### Claim 5 (depends on 2)

The fabrication method of claim 2, wherein a bottom surface of the trench is coplanar with a top surface of the substrate.

### Claim 6 (depends on 2)

The fabrication method of claim 2, wherein a first source/drain region is directly connected to the second dielectric on the first sidewall of the dielectric pillar and a second source/drain region is directly connected to the second dielectric on the second sidewall of the dielectric pillar.

### Claim 7 (depends on 2)

The fabrication method of claim 2, wherein the first dielectric is in direct contact with each of the pair of replacement gate structures.

### Claim 8

A forksheet semiconductor device comprising:
a first side separated from a second side by a dual dielectric pillar that comprises a first sidewall that faces the first side, a second sidewall that faces the second side, a first dielectric, and a second dielectric that is different from the first dielectric;
a first source/drain region within the first side that is directly connected to the second dielectric of the first sidewall of the dual dielectric pillar;
a second source/drain region within the second side that is directly connected to the second dielectric of the second sidewall of the dual dielectric pillar; and
an in-line gate structure comprising a first gate within the first side and a second gate within the second side, wherein the first gate is directly connected to the first dielectric of the first sidewall of the dual dielectric pillar and the second gate is directly connected to the first dielectric of the second sidewall of the dual dielectric pillar.

### Claim 9 (depends on 8)

The forksheet semiconductor device of claim 8, wherein the in-line gate structure further comprises a conductive gate connector directly upon the first dielectric that is directly connected to the first gate and is directly connected to the second gate.

### Claim 10 (depends on 8)

The forksheet semiconductor device of claim 8, wherein the first source/drain region is further directly connected to the first dielectric of the first sidewall of the dual dielectric pillar and wherein the second source/drain region is further directly connected to the first dielectric of the second sidewall of the dual dielectric pillar.

### Claim 11 (depends on 8)

The forksheet semiconductor device of claim 8, further comprising:
a first plurality of channel nanosheets within the first side that are directly connected to the first dielectric of the first sidewall of the dual dielectric pillar; and
a second plurality of channel nanosheets within the second side that are directly connected to the first dielectric of the second sidewall of the dual dielectric pillar.

### Claim 12 (depends on 9)

The forksheet semiconductor device of claim 9, wherein a bottom surface of the conductive gate connector is above a bottom surface of the second dielectric.

### Claim 13 (depends on 8)

The forksheet semiconductor device of claim 8, wherein the first dielectric has etch selectivity relative to the second dielectric.

### Claim 14

A forksheet nanosheet semiconductor device comprising:
a dual dielectric pillar comprising a sidewall, a first dielectric, and a second dielectric different than the first dielectric;
a plurality of first channel nanosheets that directly contact the first dielectric of the sidewall of the dual dielectric pillar;
a first source/drain region that directly contacts the plurality of channel nanosheets and that directly contacts the second dielectric of the sidewall of the dual dielectric pillar; and
a gate that directly contacts the plurality of channel nanosheets and that directly contacts the first dielectric of the sidewall of the dual dielectric pillar.

### Claim 15 (depends on 14)

The forksheet nanosheet semiconductor device of claim 14, further comprising:
a second source/drain region that directly contacts the plurality of channel nanosheets and that directly contacts the second dielectric on the sidewall of the dual dielectric pillar.

### Claim 16 (depends on 15)

The forksheet nanosheet semiconductor device of claim 15, wherein the first source/drain region directly contacts a first region of the second dielectric and wherein the second source/drain region directly contacts a second region of the second dielectric.

### Claim 17 (depends on 16)

The forksheet nanosheet semiconductor device of claim 16, wherein the dual dielectric pillar further comprises a gate connector that directly contacts the first region of the second dielectric, that directly contacts the second region of the second dielectric, and that directly contacts the first dielectric.

### Claim 18 (depends on 17)

The forksheet nanosheet semiconductor device of claim 17, wherein the gate connector further directly contacts the gate.

### Claim 19 (depends on 14)

The forksheet nanosheet semiconductor device of claim 14, wherein the dual dielectric pillar further comprises a top surface that is coplanar with a top surface of the gate.

### Claim 20 (depends on 14)

The forksheet nanosheet semiconductor device of claim 14 wherein the dual dielectric pillar further comprises a bottom surface that is below a bottom surface of the first source/drain region.