# US 12,002,807 B2 · Semiconductor structure

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,002,807 B2
- Document ID: US12002807B2
- Status: Granted
- Kind: B2
- Application number: 17/844,081
- Filed: 2022-06-20
- Published: 2022-10-06
- Granted: 2024-06-04
- Earliest claimed: 2020-04-01
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Jing-Jung Huang; Ching En Chen; Jung-Hui Kao; Kong-Beng Thei
- Web page: https://patentgrep.com/patent/US12002807B2

## CPC

- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 64/514: {characterised by the insulating layers}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 84/0156: {Manufacturing their doped wells}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a substrate including a first region and a second region; a first device disposed in the first region and a second device disposed in the second region; a first isolation disposed in the first region, wherein the first isolation is between a first source and a first drain, a first spacer overlaps the first isolation, the first isolation is separated from the first spacer by a first gate dielectric.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate comprising a first region and a second region;
a first device disposed in the first region and a second device disposed in the second region, wherein the first device comprises a first source, a first drain, a first gate dielectric, a first gate, and a pair of spacers, the first gate includes a first sidewall and a second sidewall opposite to the first sidewall, the first gate dielectric includes a third sidewall proximal to the first sidewall and a fourth sidewall opposite to the third sidewall, a first spacer of the pair of spacers lines the first sidewall and the third sidewall, and a second spacer of the pair of spacers lines the second sidewall and is separated from the fourth sidewall;
a first isolation disposed in the first region, wherein the first isolation is between the first source and the first drain, the second spacer overlaps the first isolation, the first isolation is separated from the second spacer by the first gate dielectric; and
a second isolation in the first region and adjacent to the first device, wherein a depth of the second isolation is less than a depth of the first isolation.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein a size of the first gate of the first device is greater than a size of a second gate of the second device.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the second device further comprises a second gate dielectric, and a thickness of the first gate dielectric is greater than a thickness of the second gate dielectric.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, further comprising:
a third isolation disposed in the second region, wherein a depth of the third isolation is less than a depth of the first isolation.

### Claim 5 (depends on 4)

The semiconductor structure of claim 4, wherein a first width of the first isolation is greater than a second width of the third isolation.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein an area of the first region is greater than an area of the second region.

### Claim 7

A semiconductor structure, comprising:
a semiconductor substrate;
a first device disposed in a first region, wherein the first device comprises a first spacer, and a second spacer coupled to the first spacer, and a height of the first spacer is less than a height of the second spacer;
a first isolation in the first region,
wherein the first device overlaps the first isolation, the first spacer has a first sidewall and a second sidewall coupled with the first sidewall, the first sidewall and the second sidewall of the first spacer overlap the first isolation; and
a second isolation in the first region and adjacent to the first device, wherein a depth of the second isolation is less than a depth of the first isolation.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein the first device comprises a first gate dielectric, the first gate dielectric has a first portion over the semiconductor substrate and a second portion over the first isolation, and the second portion is thicker than the first portion.

### Claim 9 (depends on 7)

The semiconductor structure of claim 7, further comprising:
a second device disposed in a second region adjacent to the first region, wherein a voltage level of the first device is greater than a voltage level of the second device.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, further comprising:
a third isolation in the second region and adjacent to the second device, wherein a depth of the third isolation is less than a depth of the first isolation.

### Claim 11 (depends on 10)

The semiconductor structure of claim 10, wherein a top surface of the first isolation and a top surface of the third isolation are substantially on a same level.

### Claim 12

A semiconductor structure, comprising:
a first isolation, disposed in a first region of a substrate, wherein the first isolation comprises a first width and a first depth; and
a second isolation, disposed in the first region of the substrate and being adjacent to the first isolation, wherein the second isolation comprises a second width less than the first width, and a second depth less than the first depth;
a first device, disposed over the first region of the substrate and including a first gate dielectric layer, a first spacer and a second spacer, wherein the first device is separated from a vertical projection of the second isolation and overlaps the first isolation, the first gate dielectric layer has a first portion covers the substrate and a second portion covers the first isolation, the first spacer lines a sidewall of the first portion, the second spacer is disposed over the second portion and separated from a sidewall of the second portion, a height of the first spacer is greater than a height of the second spacer, and the first portion is thinner than the second portion.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, wherein the first isolation is between a first source and a first drain of the first device.

### Claim 14 (depends on 13)

The semiconductor structure of claim 13, wherein the first source is between the first isolation and the second isolation.

### Claim 15 (depends on 12)

The semiconductor structure of claim 12, wherein the first device further includes a first gate electrode disposed over the first gate dielectric layer, and the first spacer and the second spacer are disposed on two opposite sidewalls of the first gate electrode.

### Claim 16 (depends on 15)

The semiconductor structure of claim 15, wherein the second spacer overlaps the first isolation, and the first spacer is separated from a vertical projection of the first isolation.

### Claim 17 (depends on 12)

The semiconductor structure of claim 12, wherein the semiconductor structure further comprises:
a second device, disposed over a second region of the substrate, wherein the second region is adjacent to the first region; and
a third isolation, disposed in the second region of the substrate, wherein the third isolation has a depth less than the first depth of the first isolation.

### Claim 18 (depends on 17)

The semiconductor structure of claim 17, wherein the second device comprises a second gate dielectric layer and a second gate electrode disposed over the second gate dielectric layer, and a thickness of the first gate dielectric layer is greater than a thickness of the second gate dielectric layer.

### Claim 19 (depends on 8)

The semiconductor structure of claim 8, wherein the first gate dielectric layer is free from overlapping a drain of the first device.

### Claim 20 (depends on 17)

The semiconductor structure of claim 17, wherein the depth of the third isolation is less than the depth of the depth of the second isolation.