# US 12,002,805 B2 · Local vertical interconnects for monolithic stack transistors

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- Number: US 12,002,805 B2
- Document ID: US12002805B2
- Status: Granted
- Kind: B2
- Application number: 17/445,013
- Filed: 2021-08-13
- Published: 2023-02-16
- Granted: 2024-06-04
- Earliest claimed: 2021-08-13
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Heng Wu; Ruilong Xie; Chen Zhang; Eric Miller
- Web page: https://patentgrep.com/patent/US12002805B2

## CPC

- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 88/01: {Manufacture or treatment}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/082: {the openings being tapered via holes}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming a stacked transistor includes forming a sacrificial cap over a first interconnect of a lower level transistor. The method further includes forming an upper level transistor above the sacrificial cap. The method further includes removing the sacrificial cap to form an opening such that the opening is delimited by the upper level transistor. The method further includes forming a second interconnect in the opening such that the second interconnect is in direct contact with the first interconnect.

## Claims

### Claim 1

A semiconductor device, comprising:
a lower level transistor including a first source, a first drain, a first interconnect in direct contact with one of the first source and the first drain, and a second interconnect in direct contact with the other of the first source and the first drain;
an upper level transistor including a second source, a second drain, a third interconnect in direct contact with one of the second source and the second drain, and a fourth interconnect in direct contact with the other of the second source and the second drain;
a dielectric layer arranged between the lower level transistor and the upper level transistor, the dielectric layer including a recess extending to the second interconnect; and
a dielectric cap formed in the recess and arranged in direct contact with the second interconnect,
wherein the first interconnect and the second interconnect are arranged between the lower level transistor and the upper level transistor.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the second interconnect is separated from the fourth interconnect by the dielectric cap and by the other of the second source and the second drain.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the third interconnect is in direct contact with the first interconnect.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the third interconnect surrounds the one of the second source and the second drain.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein:
the third interconnect is in direct contact with a first surface, a second surface, and a third surface of the one of the second source and the second drain, the first surface, the second surface, and the third surface facing in different directions than one another.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the second interconnect is separated from the fourth interconnect by the dielectric cap and by the other of the second source and the second drain.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, wherein the third interconnect is in direct contact with the first interconnect.