# US 12,002,803 B2 · Semiconductor device, electronic system, and electrostatic discharge protection method for semiconductor device thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,002,803 B2
- Document ID: US12002803B2
- Status: Granted
- Kind: B2
- Application number: 18/196,090
- Filed: 2023-05-11
- Published: 2023-09-14
- Granted: 2024-06-04
- Earliest claimed: 2021-08-06
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Chun-Lu Lee
- Web page: https://patentgrep.com/patent/US12002803B2

## CPC

- H10D 89/911: {using passive elements as protective elements}
- H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60)
- H10B 12/50: {Peripheral circuit region structures}
- H10D 89/931: {characterised by the dispositions of the protective arrangements}
- H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)}
- H10W 90/00: Package configurations
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

The present application discloses a semiconductor device, an electronic system and an electrostatic discharge (ESD) protection method for a semiconductor device thereof. The semiconductor device includes a substrate, an operation solder structure disposed on a first surface of the substrate for receiving an operation signal, a detection solder structure disposed on the first surface of the substrate for receiving a chip connection signal, and a semiconductor chip disposed on a second surface of the substrate. The semiconductor chip includes an operation electrical contact coupled to the operation solder structure, a detection electrical contact coupled to the detection solder structure, an ESD protection unit coupled to the operation electrical contact, and a logic circuit coupled to the detection electrical contact for adjusting capacitance of the ESD protection unit according to the chip connection signal.

## Claims

### Claim 1

An electrostatic discharge (ESD) protection method for a first semiconductor device, wherein the first semiconductor device comprises a substrate, an operation solder structure disposed on a first surface of the substrate, and a first semiconductor chip disposed on a second surface of the substrate, and the method comprises:
forming an ESD protection unit in the first semiconductor chip, wherein the ESD protection unit is coupled between a voltage terminal and an operation electrical contact of the first semiconductor chip coupled to the operation solder structure through the substrate, and the voltage terminal is coupled to a ground or a power voltage;
coupling the first semiconductor device to a circuit board;
transmitting an operation signal to the operation solder structure through the circuit board; and
adjusting capacitance of the ESD protection unit according to a total quantity of semiconductor chips that receive the operation signal and operate in parallel with the first semiconductor chip.

### Claim 2 (depends on 1)

The method of claim 1, wherein the ESD protection unit comprises a plurality of ESD protection elements coupled between the operation electrical contact and the voltage terminal, and adjusting the capacitance of the ESD protection unit according to the total quantity of semiconductor chips that receive the operation signal and operate in parallel with the first semiconductor chip comprises:
uncoupling at least one of the plurality of ESD protection elements from the operation electrical contact or the voltage terminal.

### Claim 3 (depends on 1)

The method of claim 1, wherein one of the semiconductor chips that receive the operation signal and operate in parallel with the first semiconductor chip is in the first semiconductor device or a second semiconductor device coupled to the first semiconductor device through the circuit board.

### Claim 4 (depends on 3)

The method of claim 3, wherein the first semiconductor device and the second semiconductor device comprise memory circuits of different ranks.