# US 12,002,801 B2 · Charging protection circuit, charging circuit, and electronic device

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- Number: US 12,002,801 B2
- Document ID: US12002801B2
- Status: Granted
- Kind: B2
- Application number: 17/852,476
- Filed: 2022-06-29
- Published: 2022-10-13
- Granted: 2024-06-04
- Earliest claimed: 2019-12-30
- Assignees: Huawei Technologies Co., Ltd.
- Applicants: Huawei Technologies Co., Ltd.
- Inventors: Huaifeng Wang; Jiangtao Yang; Hang Wang
- Web page: https://patentgrep.com/patent/US12002801B2

## CPC

- H02M 1/32: Means for protecting converters other than automatic disconnection
- H10D 89/814: {involving a parasitic bipolar transistor triggered by the electrical biasing of the gate electrode of the FET, e.g. gate coupled transistors}
- H02H 9/04: responsive to excess voltage (lightning arrestors H01C7/12, H01C8/04, H01G9/18, H01T)
- H02H 9/046: {responsive to excess voltage appearing at terminals of integrated circuits}
- H02J 7/62: against overcurrent
- H02J 7/663: {using battery or load disconnect circuits (H02J9/002 takes precedence)}
- H02M 1/0006: {Arrangements for supplying an adequate voltage to the control circuit of converters}
- H03K 17/063: {in field-effect transistor switches}
- H03K 19/00315: {in field-effect transistor circuits}
- H10D 89/611: {using diodes as protective elements}
- H10D 89/815: {involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base region of said parasitic bipolar transistor}
- H02J 2207/30: Charge provided using DC bus or data bus of a computer
- H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H03K 2017/066: {Maximizing the OFF-resistance instead of minimizing the ON-resistance}
- H03K 2217/0018: Special modifications or use of the back gate voltage of a FET
- H03K 2217/0054: Gating switches, e.g. pass gates
- H03K 2217/0081: Power supply means, e.g. to the switch driver
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)
- H02J: ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

This application relates to a charging protection circuit. The charging protection circuit implements overcurrent protection by using a four-terminal NMOS switching transistor. In the solution provided in this application, floating management is performed on a Sub port of the four-terminal NMOS switching transistor. Specifically, when the four-terminal NMOS switching transistor is turned on, potential of the Sub port is pulled up, to avoid an excessively large internal resistance of the four-terminal NMOS switching transistor caused by an excessively large voltage between the Sub port and a drain of the four-terminal NMOS switching transistor. In addition, this application further provides a charging circuit and an electronic device.

## Claims

### Claim 1

A charging protection circuit, comprising:
a first four-terminal N-type metal oxide semiconductor NMOS switching transistor, comprising a first drain, a second drain, a gate, and a Sub port, wherein the first drain is connected to a first power supply interface, the second drain is connected to a load, and the gate is connected to a drive circuit; and
a Sub port management circuit, comprising a pull-up circuit connected to the Sub port, wherein the pull-up circuit is configured to: when the first four-terminal NMOS switching transistor is turned on, pull up potential of the Sub port to potential of the first drain or the second drain, wherein:
the pull-up circuit comprises a first three-terminal NMOS switching transistor,
a drain of the first three-terminal NMOS switching transistor is connected to the first drain of the first four-terminal NMOS switching transistor, a source of the first three-terminal NMOS switching transistor is connected to the Sub port, a gate of the first three-terminal NMOS switching transistor is connected to the drive circuit, and a drive voltage provided by the drive circuit enables both the first three-terminal NMOS switching transistor and the first four-terminal NMOS switching transistor to be turned on,
a threshold voltage of the first three-terminal NMOS switching transistor and a threshold voltage of the first four-terminal NMOS switching transistor have a same value, and
the drive circuit is configured to provide a same drive voltage for the gate of the first four-terminal NMOS switching transistor and the gate of the first three-terminal NMOS switching transistor.

### Claim 2 (depends on 1)

The charging protection circuit according to claim 1, wherein the pull-up circuit further comprises a second three-terminal NMOS switching transistor; and
a drain of the second three-terminal NMOS switching transistor is connected to the second drain of the first four-terminal NMOS switching transistor, a source of the second three-terminal NMOS switching transistor is connected to the Sub port, a gate of the second three-terminal NMOS switching transistor is connected to the drive circuit, and the drive voltage provided by the drive circuit enables both the second three-terminal NMOS switching transistor and the first four-terminal NMOS switching transistor to be turned on.

### Claim 3 (depends on 2)

The charging protection circuit according to claim 2, wherein a threshold voltage of the second three-terminal NMOS switching transistor and the threshold voltage of the first four-terminal NMOS switching transistor have a same value, and the drive circuit is configured to provide drive voltages with a same phase for the gate of the first four-terminal NMOS switching transistor and the gate of the second three-terminal NMOS switching transistor.

### Claim 4 (depends on 1)

The charging protection circuit according to claim 1, wherein the Sub port management circuit further comprises a pull-down circuit, and the pull-down circuit is connected to the Sub port, and is configured to: when the first four-terminal NMOS switching transistor is turned off, pull down the potential of the Sub port to zero potential.

### Claim 5 (depends on 4)

The charging protection circuit according to claim 4, wherein the pull-down circuit comprises a third three-terminal NMOS switching transistor; and
a source of the third three-terminal NMOS switching transistor is grounded, a drain of the third three-terminal NMOS switching transistor is connected to the Sub port, a gate of the third three-terminal NMOS switching transistor is connected to the drive circuit, and a drive voltage provided by the drive circuit enables one of the third three-terminal NMOS switching transistor and the first four-terminal NMOS switching transistor to be turned on while the other is turned off.

### Claim 6 (depends on 5)

The charging protection circuit according to claim 5, wherein the drive circuit is configured to provide drive voltages with opposite phases for the gate of the third three-terminal NMOS switching transistor and the gate of the first four-terminal NMOS switching transistor.

### Claim 7 (depends on 5)

The charge protection circuit according to claim 5, wherein the drive circuit comprises a pulse width modulation PWM module and a charge pump;
a first input terminal of the charge pump is connected to an output terminal of the PWM module, and is configured to receive a control logic voltage Vpwm input by the charge pump;
a second input terminal of the charge pump is connected to the first power supply interface, and is configured to receive a bus voltage Vbus input from the first power supply interface, and an output terminal of the charge pump is connected to the gate of the first four-terminal NMOS switching transistor; and
the charge pump processes, under control of Vpwm, Vbus to obtain an output voltage Vout, and applies Vout to the gate of the first four-terminal NMOS switching transistor.

### Claim 8 (depends on 7)

The charging protection circuit according to claim 7, wherein the Sub port management circuit further comprises an inverter; one terminal of the inverter is connected to the output terminal of the PWM module, and the other terminal is connected to the gate of the third three-terminal NMOS switching transistor; and the inverter is configured to: perform phase inversion processing on Vpwm to obtain a voltage Vpwm, and apply Vpwm, to the gate of the third three-terminal NMOS switching transistor.

### Claim 9 (depends on 4)

The charging protection circuit according to claim 4, wherein the pull-down circuit comprises a pull-down resistor, a first terminal of the pull-down resistor is connected to the Sub port, and a second terminal of the pull-down resistor is grounded.

### Claim 10 (depends on 4)

The charging protection circuit according to claim 4, wherein the Sub port management circuit comprises a complementary metal oxide semiconductor CMOS switching transistor, the CMOS switching transistor comprises a P-type metal oxide semiconductor PMOS switching transistor and a fourth three-terminal NMOS switching transistor that have a common gate, the pull-up circuit comprises the PMOS switching transistor, and the pull-down circuit comprises the fourth three-terminal NMOS switching transistor, wherein a threshold voltage of the PMOS switching transistor and a threshold voltage of the fourth three-terminal NMOS switching transistor have a same value;
a source of the PMOS switching transistor is connected to the first power supply interface, a drain of the PMOS switching transistor is connected to the Sub port, a drain of the fourth three-terminal NMOS switching transistor is connected to the Sub port, and a source of the fourth three-terminal NMOS switching transistor is grounded; and
a drive voltage applied to the gate of the PMOS switching transistor and the gate of the fourth three-terminal NMOS switching transistor and a drive voltage applied to the first four-terminal NMOS switching transistor have opposite phases.

### Claim 11 (depends on 1)

The charging protection circuit according to claim 1, further comprising a second power supply interface and a second four-terminal NMOS switching transistor, one drain of the second four-terminal NMOS switching transistor is connected to the second power supply interface, and the other drain is connected between the second drain of the first four-terminal NMOS switching transistor and the load.

### Claim 12 (depends on 11)

The charging protection circuit according to claim 11, wherein the second power supply interface comprises a charging coil and a wireless interface chip, the charging coil is connected to one terminal of the wireless receiving chip, and the other terminal of the wireless interface chip is connected to any drain of the second four-terminal NMOS switching transistor.

### Claim 13 (depends on 1)

The charging protection circuit according to claim 1, wherein the first power supply interface is a universal serial bus USB port.

### Claim 14 (depends on 1)

The charging protection circuit according to claim 1, wherein the load is a battery.

### Claim 15 (depends on 1)

A charging circuit, comprising a first power supply interface, a load, and the charging protection circuit according to claim 1, wherein one terminal of the charging protection circuit is connected to the first power supply interface, the other terminal is connected to the load, and the charging protection circuit is configured to provide, for the load, power received from the first power supply interface.

### Claim 16 (depends on 15)

An electronic device, comprising the charging circuit according to claim 15 and a processor, wherein the processor is configured to obtain remaining power information of a load in the charging circuit.