# US 12,002,799 B2 · Die stacking structure and method forming same

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- Number: US 12,002,799 B2
- Document ID: US12002799B2
- Status: Granted
- Kind: B2
- Application number: 17/814,766
- Filed: 2022-07-25
- Published: 2022-11-10
- Granted: 2024-06-04
- Earliest claimed: 2020-03-12
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chen-Hua Yu; Hung-Yi Kuo; Chung-Shi Liu; Hao-Yi Tsai; Cheng-Chieh Hsieh; Tsung-Yuan Yu; Ming Hung Tseng
- Web page: https://patentgrep.com/patent/US12002799B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 90/00: Package configurations
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 70/095: {of vias therein}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon
- H10W 72/019: {of bond pads}
- H10W 72/072: {of bump connectors}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/014: {using batch processing}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7434: {used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/655: Fan-out layouts
- H10W 72/07254: {changes in dispositions}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.

## Claims

### Claim 1

A structure comprising:
a package comprising:
a first die comprising a first plurality of bonding pads;
a second die comprising:
a second plurality of bonding pads bonding to the first plurality of bonding pads;
a semiconductor substrate underlying the second plurality of bonding pads;
a plurality of through-vias penetrating through the semiconductor substrate;
first electrical connectors underlying and connecting to the plurality of through-vias; and
probe pads; and
a first encapsulant encapsulating the first die therein, wherein all sidewalls and top surfaces of the probe pads are in contact with the first encapsulant;
a second encapsulant encapsulating the package therein; and
an interconnect structure underlying the package, wherein the interconnect structure comprises:
a dielectric layer underlying and contacting both of the second encapsulant and the package; and
a plurality of redistribution lines extending into the dielectric layer to contact the first electrical connectors.

### Claim 2 (depends on 1)

The structure of claim 1, wherein the plurality of redistribution lines are formed of non-solder materials.

### Claim 3 (depends on 1)

The structure of claim 1, wherein a portion of the plurality of redistribution lines is directly underlying the second encapsulant.

### Claim 4 (depends on 1)

The structure of claim 1, wherein the first encapsulant and the second encapsulant have a distinguishable interface.

### Claim 5 (depends on 1)

The structure of claim 1 further comprising:
a package substrate underlying the interconnect structure; and
solder regions physically bonding the interconnect structure to the package substrate.

### Claim 6 (depends on 1)

The structure of claim 1, wherein the probe pads comprise copper.

### Claim 7 (depends on 1)

The structure of claim 1, wherein first top surfaces of the second plurality of bonding pads are coplanar with second top surfaces of the probe pads.

### Claim 8

A structure comprising:
a package comprising:
a device die comprising:
a semiconductor substrate;
a probe pad; and
a solder region over and contacting the probe pad;
a package component over and bonding to the device die;
a first molding compound molding the package component therein, wherein all sidewalls and an entire top surface of the solder region are in direct contact with the first molding compound;
a dielectric layer underlying the device die, wherein edges of the dielectric layer are flush with corresponding edges of the first molding compound and the device die; and
non-solder conductive features underlying the semiconductor substrate of the device die, wherein the non-solder conductive features extend into the dielectric layer; and
a plurality of redistribution lines underlying and physically contacting the non-solder conductive features, wherein the plurality of redistribution lines are distributed in an area laterally extending beyond corresponding first edges of the package.

### Claim 9 (depends on 8)

The structure of claim 8 further comprising:
a second molding compound encircling the package; and
a plurality of dielectric layers, wherein the plurality of redistribution lines extend into the plurality of dielectric layers, and wherein second edges of the second molding compound are flush with corresponding third edges of the plurality of dielectric layers.

### Claim 10 (depends on 9)

The structure of claim 9, wherein the second molding compound comprises a portion directly underlying the dielectric layer, and the second molding compound is in physical contact with the non-solder conductive features.

### Claim 11 (depends on 8)

The structure of claim 8 further comprising a polymer layer in the package and encapsulating the non-solder conductive features therein, wherein additional edges of the polymer layer are flush with the corresponding edges of the first molding compound and corresponding fourth edges of the device die.

### Claim 12 (depends on 8)

The structure of claim 8, wherein the device die comprises electrical conductive features, and wherein the electrical conductive features comprise top surfaces and sidewalls contacting the first molding compound.

### Claim 13 (depends on 8)

The structure of claim 8, wherein the plurality of redistribution lines comprise:
via portions physically contacting the non-solder conductive features; and
trace portions joined to respective ones of the vias portions, wherein the trace portions are underlying the via portions.

### Claim 14 (depends on 8)

The structure of claim 8, wherein the non-solder conductive features comprise metal pillars.

### Claim 15 (depends on 8)

The structure of claim 8, wherein the probe pad comprises copper.

### Claim 16 (depends on 8)

The structure of claim 8, wherein the dielectric layer comprises a polymer.

### Claim 17

A structure comprising:
a first device die comprising:
a semiconductor substrate;
a first plurality of electrical connectors over the semiconductor substrate; and
a second plurality of electrical connectors over the semiconductor substrate, wherein both of a first one and a second one of the second plurality of electrical connectors comprises:
a metal pillar; and
a solder region over the metal pillar;
a second device die over and bonding to the first device die through the first plurality of electrical connectors; and
a first molding compound molding the second device die and the second plurality of electrical connectors therein, wherein the second plurality of electrical connectors are overlapped by, and are in physical contact with, the first molding compound molding, wherein an entire top surface of the solder region is in contact with the first molding compound.

### Claim 18 (depends on 17)

The structure of claim 17, wherein edges of the first molding compound are flush with corresponding edge of the first device die, and the structure further comprises a second molding compound molding the first molding compound and the first device die therein.

### Claim 19 (depends on 18)

The structure of claim 18, wherein the second molding compound extends directly underlying, and contacting a bottom surface of, the first device die.

### Claim 20 (depends on 17)

The structure of claim 17, wherein the second plurality of electrical connectors are located on opposite sides of the first plurality of electrical connectors.