# US 12,002,793 B2 · Integrating system in package (SiP) with input/output (IO) board for platform miniaturization

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- Number: US 12,002,793 B2
- Document ID: US12002793B2
- Status: Granted
- Kind: B2
- Application number: 17/392,189
- Filed: 2021-08-02
- Published: 2021-11-25
- Granted: 2024-06-04
- Earliest claimed: 2019-08-20
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Eng Huat Goh; Wee Hoe; Khang Choong Yong; Ping Ping Ooi
- Web page: https://patentgrep.com/patent/US12002793B2

## CPC

- H10W 90/00: Package configurations
- H05K 1/144: {Stacked arrangements of planar printed circuit boards}
- H05K 1/147: {at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit (H05K1/148 takes precedence)}
- H05K 1/181: associated with surface mounted components
- H05K 3/303: with surface mounted components (H05K3/32 takes precedence)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/00: Interconnections or connectors in packages
- H05K 2201/048: Second PCB mounted on first PCB by inserting in window or holes of the first PCB
- H05K 2201/055: Folded back on itself
- H05K 2201/1003: Non-printed inductor
- H05K 2201/10098: Components for radio transmission, e.g. radio frequency identification [RFID] tag, printed or non-printed antennas
- H05K 2201/10151: Sensor
- H05K 2201/10159: Memory
- H05K 2201/10356: Cables
- H05K 2201/10522: Adjacent components
- H05K 2201/10545: Related components mounted on both sides of the PCB
- H05K 2201/10704: Pin grid array [PGA]
- H05K 2201/10719: Land grid array [LGA]
- H05K 2201/10734: Ball grid array [BGA]; Bump grid array
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.

## Claims

### Claim 1

A computing system comprising:
a processor having one or more processor cores;
a volatile memory coupled to the processor to store data to be processed by the processor;
a System in Package (SiP) board, wherein the SiP board comprises a plurality of logic components, wherein the plurality of logic components comprises the processor and the volatile memory; and
an Input Output (IO) board coupled to the SiP board via a grid array,
wherein the plurality of logic components is to be provided on both a first side and a second side of the SiP board, wherein one or more of the plurality of logic components are to be positioned in an opening in the IO board, wherein the opening in the IO board is to be formed by a location of one or more components of the SiP board, wherein at least one flexible cable is to couple a first logic component of the plurality of logic components on the first side of the SiP board to a second logic component of the plurality of logic components on the second side of the SiP board, wherein a non-volatile memory is to be mounted to the IO board.

### Claim 2 (depends on 1)

The computing system of claim 1, wherein the non-volatile memory comprises a solid state drive.

### Claim 3 (depends on 1)

The computing system of claim 1, wherein the grid array comprises one or more of: land grid array, ball grid array, pin grid array, and solder grid array.

### Claim 4 (depends on 1)

The computing system of claim 1, wherein a height of the one or more of the plurality of logic components is not to exceed beyond a surface formed by a side of the IO board that faces away from a coupling formed by the grid array.

### Claim 5 (depends on 1)

The computing system of claim 1, wherein the IO board comprises one or more logic components on a first side of the IO board, wherein the first side of the IO board is to be coupled to the SiP board via the grid array.

### Claim 6 (depends on 1)

The computing system of claim 1, wherein the IO board comprises one or more logic components on a first side and a second side of the IO board.

### Claim 7 (depends on 1)

The computing system of claim 1, wherein the first side of the SiP board comprises all of the plurality of logic components with a lower profile and the second side of the SiP board comprises all of the plurality of logic components with a taller profile.

### Claim 8 (depends on 1)

The computing system of claim 1, wherein the IO board comprises one or more logic components on a first side and a second side of the IO board, wherein the first side of the IO board comprises all of the one or more logic components with a lower profile and the second side of the IO board comprises all of the one or more logic components with a taller profile.