# US 12,002,788 B2 · Bonded semiconductor devices having processor and dynamic random-access memory and methods for forming the same

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- Number: US 12,002,788 B2
- Document ID: US12002788B2
- Status: Granted
- Kind: B2
- Application number: 18/083,198
- Filed: 2022-12-16
- Published: 2023-04-20
- Granted: 2024-06-04
- Earliest claimed: 2019-04-15
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Jun Liu; Weihua Cheng
- Web page: https://patentgrep.com/patent/US12002788B2

## CPC

- H10W 90/00: Package configurations
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells}
- H03K 19/17744: {for input/output signals}
- H10B 10/12: {comprising a MOSFET load element}
- H10B 10/18: {Peripheral circuit regions}
- H10B 12/02: {for one transistor one-capacitor [1T-1C] memory cells}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/50: {Peripheral circuit region structures}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/30: Die-attach connectors
- H10W 80/00: Direct bonding of chips, wafers or substrates
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- H10B 10/00: Static random access memory [SRAM] devices
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 72/01: {Manufacture or treatment}
- H10W 72/019: {of bond pads}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/07331: {Connecting techniques}
- H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/552: {comprising metals or metalloids, e.g. silver}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/5525: {comprising copper [Cu]}
- H10W 72/90: Bond pads, in general
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/951: {Materials of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 80/016: {Cleaning}
- H10W 80/041: {Thermally treating}
- H10W 80/211: {using auxiliary members, e.g. aids for protecting the bonding area}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/732: {having shape changed during the connecting}
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/20: Configurations of stacked chips
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, first semiconductor structures are formed. At least one of the first semiconductor structures includes a processor, static random-access memory (SRAM) cells, and a first bonding layer comprising first bonding contacts. Second semiconductor structures are formed. At least one of the second semiconductor structures comprises dynamic random-access memory (DRAM) cells and a second bonding layer comprising second bonding contacts. The first semiconductor structures and the second semiconductor structures are bonded. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure. At least one of the first semiconductor structures and the second semiconductor structures further includes a peripheral circuit.

## Claims

### Claim 1

A method for forming a semiconductor device, comprising:
forming first semiconductor structures, wherein at least one of the first semiconductor structures comprises a processor, static random-access memory (SRAM) cells, and a first bonding layer comprising first bonding contacts;
forming second semiconductor structures, wherein at least one of the second semiconductor structures comprises dynamic random-access memory (DRAM) cells and a second bonding layer comprising second bonding contacts; and
bonding the first semiconductor structures and the second semiconductor structures,
wherein the first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure; and
wherein at least one of the first semiconductor structures and the second semiconductor structures further comprises a peripheral circuit, and the peripheral circuit comprises an input/output buffer, a decoder, and a sense amplifier configured to facilitate operations of the DRAM cells in the at least one of the second semiconductor structures.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the first semiconductor structures comprises:
forming the processor and the SRAM cells on a first wafer; and
the SRAM cells is outside of the processor.

### Claim 3 (depends on 2)

The method of claim 2, wherein forming the second semiconductor structures comprises:
forming the DRAM cells on a second wafer.

### Claim 4 (depends on 3)

The method of claim 3, wherein bonding the first semiconductor structures and the second semiconductor structures comprises:
bonding the first wafer and the second wafer.

### Claim 5 (depends on 4)

The method of claim 4, further comprising,
dicing the bonded first and second wafers into a plurality of dies, wherein at least one of the dies comprises the bonded first and second semiconductor structures.

### Claim 6 (depends on 3)

The method of claim 3, wherein bonding the first semiconductor structures and the second semiconductor structures comprises:
dicing the first wafer into a plurality of first dies, such that at least one of the first dies comprises the at least one of the first semiconductor structures;
dicing the second wafer into a plurality of second dies, such that at least one of the second dies comprises the at least one of the second semiconductor structures; and
bonding the first die and the second die.

### Claim 7 (depends on 2)

The method of claim 2, wherein forming the first semiconductor structures comprises:
forming a first interconnect layer above the processor and the SRAM cells; and
forming the first bonding layer above the first interconnect layer.

### Claim 8 (depends on 2)

The method of claim 2, wherein forming the processor and the SRAM cells comprises forming transistors on the first wafer.

### Claim 9 (depends on 2)

The method of claim 2, wherein forming the first semiconductor structures further comprises forming the peripheral circuit of the DRAM cells on the first wafer.

### Claim 10 (depends on 9)

The method of claim 9, wherein the peripheral circuit on the first wafer is outside of the processor.

### Claim 11 (depends on 3)

The method of claim 3, wherein forming the second semiconductor structures comprises:
forming a second interconnect layer above the DRAM cells; and
forming the second bonding layer above the second interconnect layer.

### Claim 12 (depends on 3)

The method of claim 3, wherein forming the DRAM cells comprises:
forming transistors on the second wafer; and
forming capacitors above and in contact with at least some of the transistors.

### Claim 13 (depends on 3)

The method of claim 3, wherein forming the second semiconductor structures further comprises forming the peripheral circuit of the DRAM cells on the second wafer.

### Claim 14 (depends on 13)

The method of claim 13, wherein the peripheral circuit on the second wafer is outside of the DRAM cells.

### Claim 15 (depends on 3)

The method of claim 3, wherein the second semiconductor structure is above the first semiconductor structure after the bonding.

### Claim 16 (depends on 15)

The method of claim 15, further comprising, after the bonding and prior to the dicing:
thinning the second wafer to form a semiconductor layer; and
forming a pad-out interconnect layer above the semiconductor layer.

### Claim 17 (depends on 3)

The method of claim 3, wherein the first semiconductor structure is above the second semiconductor structure after the bonding.

### Claim 18 (depends on 17)

The method of claim 17, further comprising, after the bonding and prior to the dicing:
thinning the first wafer to form a semiconductor layer; and
forming a pad-out interconnect layer above the semiconductor layer.

### Claim 19 (depends on 1)

The method of claim 1, wherein the bonding comprises hybrid bonding.