# US 12,002,787 B2 · Multi-die package structure and multi-die co-packing method

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- Number: US 12,002,787 B2
- Document ID: US12002787B2
- Status: Granted
- Kind: B2
- Application number: 17/545,229
- Filed: 2021-12-08
- Published: 2022-06-30
- Granted: 2024-06-04
- Earliest claimed: 2020-12-30
- Assignees: Chengdu Monolithic Power Systems Co., Ltd.
- Applicants: Chengdu Monolithic Power Systems Co., Ltd.
- Inventors: Yingjiang Pu; Hunt Jiang
- Web page: https://patentgrep.com/patent/US12002787B2

## CPC

- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/50: Bond wires
- H10W 74/01: Manufacture or treatment
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/63: Vias, e.g. via plugs
- H10W 72/073: {of die-attach connectors}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9413: {on encapsulations}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A multi-die package structure with an embedded die embedded in a substrate, a flip chip die mounted above the substrate, and an attached die attached onto the flip chip die. The package is compact and low cost.

## Claims

### Claim 1

A multi-die package structure, comprising:
a first die embedded in a substrate;
a second die mounted above the substrate, the second die being electrically coupled to the substrate by way of a conductor; and
a third die attached onto the second die, the third die being configured to contact with the substrate by way of a bonding wire.

### Claim 2 (depends on 1)

The multi-die package structure of claim 1, wherein the first die has an active surface, and the active surface is at least partly overlapped by the second die.

### Claim 3 (depends on 1)

The multi-die package structure of claim 1, wherein the first die has an active surface facing up to the second die, and the active surface is electrically coupled to the substrate and the second die by way of the conductor.

### Claim 4 (depends on 3)

The multi-die package structure of claim 3, wherein the conductor comprises a contact bump, a via structure and a metal trace.

### Claim 5

A multi-die co-packed chip, comprising:
an input pin, electrically coupled to a first die on which a high side power switch is fabricated;
a switch pin, electrically coupled to the first die and a second die on which a low side power switch is fabricated;
a ground pin, electrically coupled to the second die; and
a control pin, electrically coupled to a third die on which a control circuit is fabricated;
wherein any one of the first die, the second die or the third die is embedded in a substrate as an embedded die; and
wherein either one of the remaining two dies is mounted above the substrate as a flip chip die; and
the remaining die is attached onto the flip chip die as an attached die.

### Claim 6 (depends on 5)

The multi-die co-packed chip of claim 5, wherein:
the embedded die has an active surface at least partly overlapped with partial periphery of the flip chip die in a direction vertical to the active surface.

### Claim 7 (depends on 5)

The multi-die co-packed chip of claim 5, wherein:
the flip chip die is electrically coupled to the substrate and the embedded die by way of a conductor.

### Claim 8 (depends on 5)

The multi-die co-packed chip of claim 5, wherein:
the attached die is electrically coupled to the substrate by way of a wire bonding.

### Claim 9

A multi-die co-packing method, comprising:
embedding a first die in a substrate, the substrate having multiple metal layers;
mounting a second die over the substrate;
attaching a third die onto the second die;
electrically coupling the first die to the second die and the substrate by way of a conductor; and electrically coupling the third die to the substrate by way of a bonding wire; and
molding the first die, the second die, the third die, and the substrate as a package.

### Claim 10 (depends on 9)

The multi-die co-packing method of claim 9, wherein:
the first die has an active surface, and the active surface is at least partly overlapped by the second die.

### Claim 11 (depends on 10)

The multi-die co-packing method of claim 10, wherein: the conductor comprises a contact bump, a via structure or a metal trace.

### Claim 12 (depends on 10)

The multi-die co-packing method of claim 10, wherein: the conductor comprises a contact bump and a through via.