# US 12,002,784 B2 · Semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,784 B2 - Document ID: US12002784B2 - Status: Granted - Kind: B2 - Application number: 17/983,018 - Filed: 2022-11-08 - Published: 2023-02-23 - Granted: 2024-06-04 - Earliest claimed: 2020-02-28 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Yun Seok Choi - Web page: https://patentgrep.com/patent/US12002784B2 ## CPC - H10W 90/00: Package configurations - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 70/611: {for connecting multiple chips together} - H10W 70/635: {Through-vias} - H10W 70/685: comprising multiple insulating layers - H10W 72/072: {of bump connectors} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 40/70: Fillings or auxiliary members in containers or in encapsulations for thermal protection or control - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/07254: {changes in dispositions} - H10W 72/073: {of die-attach connectors} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/247: {Dispositions of multiple bumps} - H10W 72/251: {Materials} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/30: Die-attach connectors - H10W 72/325: {Die-attach connectors having a filler embedded in a matrix} - H10W 72/351: {Materials of die-attach connectors} - H10W 72/354: {comprising polymers} - H10W 72/874: {On different surfaces} - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/944: {Dispositions of multiple bond pads} - H10W 72/951: {Materials of bond pads} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes an upper substrate having a first surface and a second surface which are opposite to each other, a lower semiconductor chip disposed on the first surface of the upper substrate, a plurality of conductive pillars disposed on the first surface of the upper substrate at at least one side of the lower semiconductor chip, and an upper semiconductor chip disposed on the second surface of the upper substrate. The lower semiconductor chip and the plurality of conductive pillars are connected to the first surface of the upper substrate, and the upper semiconductor chip is connected to the second surface of the upper substrate. ## Claims ### Claim 1 A semiconductor package comprising: an upper substrate having a first surface and a second surface opposite to each other, a lower semiconductor chip on the first surface of the upper substrate; a plurality of conductive pillars on the first surface of the upper substrate and at least one side of the lower semiconductor chip; a lower mold layer on the first surface of the upper substrate, the lower mold layer filling a space between the lower semiconductor chip and the plurality of conductive pillars; a plurality of upper semiconductor chips on the second surface of the upper substrate, the plurality of upper semiconductor chips include a first upper semiconductor chip and a second upper semiconductor chip laterally spaced apart from each other in a first direction parallel to the second surface of the upper substrate and electrically connected to the second surface of the upper substrate; upper bumps between the first upper semiconductor chip and the second surface of the upper substrate and the second upper semiconductor chip and the second surface of the upper substrate; and upper underfill layers respectively disposed between the first upper semiconductor chip and the second surface of the upper substrate and the second upper semiconductor chip and the second surface of the upper substrate, wherein the lower semiconductor chip vertically overlaps a portion of the first upper semiconductor chip and a portion of the second upper semiconductor chip in a second direction perpendicular to the second surface of the upper substrate, wherein the lower semiconductor chip includes lower through-electrodes penetrating therethrough, one of the lower through-electrodes vertically overlaps the portion of the first upper semiconductor chip in the second direction, and another of the lower through-electrodes vertically overlaps the portion of the second upper semiconductor chip in the second direction, wherein the upper underfill layers are laterally spaced apart from each other in the first direction, and each of the upper underfill layers covers corresponding ones of the upper bumps, wherein the lower semiconductor chip and the plurality of conductive pillars are electrically connected to the first surface of the upper substrate. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the upper substrate is a redistribution substrate including redistribution patterns. ### Claim 3 (depends on 2) The semiconductor package of claim 2, wherein each of the plurality of upper semiconductor chips is electrically connected to the lower semiconductor chip and the plurality of conductive pillars through the redistribution patterns. ### Claim 4 (depends on 2) The semiconductor package of claim 2, wherein the plurality of upper semiconductor chips are electrically connected to each other. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein at least one of the first and second upper semiconductor chips is a High Bandwidth Memory chip which includes a plurality of memory chips stacked in a second direction perpendicular to the first direction. ### Claim 6 (depends on 1) The semiconductor package of claim 1, further comprising: a lower redistribution layer spaced apart from the first surface of the upper substrate in the first direction, wherein the lower semiconductor chip, the plurality of conductive pillars and the lower mold layer are interposed between the lower redistribution layer and the upper substrate. ### Claim 7 (depends on 6) The semiconductor package of claim 6, wherein the lower semiconductor chip and the plurality of conductive pillars are electrically connected to a surface of the lower redistribution layer. ### Claim 8 (depends on 7) The semiconductor package of claim 7, wherein the lower redistribution layer includes redistribution pads adjacent to an opposite surface of the lower redistribution layer, and no portion of the lower redistribution layer extends onto a surface of each of the redistribution pads. ### Claim 9 (depends on 8) The semiconductor package of claim 8, further comprising: connection bumps respectively disposed on the redistribution pads. ### Claim 10 (depends on 1) The semiconductor package of claim 1, wherein the upper substrate includes first upper substrate pads adjacent to the first surface and second upper substrate pads adjacent to the second surface, wherein the lower semiconductor chip is connected to a first group of the first upper substrate pads and the plurality of conductive pillars are connected to a second group of the first upper substrate pads, and wherein widths of the first group of the first upper substrate pads are different from widths of the second group of the first upper substrate pads. ### Claim 11 (depends on 10) The semiconductor package of claim 10, wherein the widths of the second group of the first upper substrate pads are greater than the widths of the first group of the first upper substrate pads. ### Claim 12 (depends on 1) The semiconductor package of claim 1, wherein the upper substrate includes first upper substrate pads adjacent to the first surface and second upper substrate pads adjacent to the second surface, wherein the lower semiconductor chip is connected to a first group of the first upper substrate pads and the plurality of conductive pillars are connected to a second group of the first upper substrate pads, and wherein a pitch of the first group of the first upper substrate pads is different from a pitch of the second group of the first upper substrate pads. ### Claim 13 (depends on 12) The semiconductor package of claim 12, wherein the pitch of the second group of the first upper substrate pads is greater than the pitch of the first group of the first upper substrate pads. ### Claim 14 A semiconductor package comprising: an upper substrate having a first surface and a second surface opposite to each other; a lower semiconductor chip on the first surface of the upper substrate; a lower mold layer on the first surface of the upper substrate, the lower mold layer covering the lower semiconductor chip; and a plurality of upper semiconductor chips on the second surface of the upper substrate, the plurality of upper semiconductor chips include a first upper semiconductor chip and a second upper semiconductor chip laterally spaced apart from each other in a first direction parallel to the second surface of the upper substrate, wherein the lower semiconductor chip is electrically connected to the first surface of the upper substrate, wherein the first and second upper semiconductor chips are different kinds of semiconductor chips and are electrically connected to the second surface of the upper substrate, wherein the lower semiconductor chip vertically overlaps a portion of the first upper semiconductor chip and a portion of the second upper semiconductor chip in a second direction perpendicular to the second surface of the upper substrate, and wherein the lower semiconductor chip includes lower through-electrodes penetrating therethrough, one of the lower through-electrodes vertically overlaps the portion of the first upper semiconductor chip in the second direction, and another of the lower through-electrodes vertically overlaps the portion of the second upper semiconductor chip in the second direction. ### Claim 15 (depends on 14) The semiconductor package of claim 14, wherein the plurality of upper semiconductor chips are electrically connected to the lower semiconductor chip through the upper substrate. ### Claim 16 (depends on 14) The semiconductor package of claim 14, wherein the plurality of upper semiconductor chips are electrically connected to each other through the upper substrate. ### Claim 17 (depends on 14) The semiconductor package of claim 14, further comprising: upper bumps between the first upper semiconductor chip and the second surface of the upper substrate and the second upper semiconductor chip and the second surface of the upper substrate; and upper underfill layers respectively disposed between the first upper semiconductor chip and the second surface of the upper substrate and the second upper semiconductor chip and the second surface of the upper substrate, wherein the upper underfill layers are laterally spaced apart from each other in the first direction, and each of the upper underfill layers covers corresponding ones of the upper bumps. ### Claim 18 (depends on 14) The semiconductor package of claim 14, wherein at least one of the first and second upper semiconductor chips is a High Bandwidth Memory chip which includes a plurality of memory chips stacked in the second direction.