# US 12,002,783 B2 · Methods of manufacturing semiconductor device with bump interconnection

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,002,783 B2
- Document ID: US12002783B2
- Status: Granted
- Kind: B2
- Application number: 17/548,205
- Filed: 2021-12-10
- Published: 2023-02-02
- Granted: 2024-06-04
- Earliest claimed: 2021-08-02
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Jun Yong Song; Kang Hun Kim; Si Yun Kim
- Web page: https://patentgrep.com/patent/US12002783B2

## CPC

- H10W 72/072: {of bump connectors}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/90: Bond pads, in general
- H10W 72/01208: {using permanent auxiliary members, e.g. using solder flow barriers, spacers or alignment marks}
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01255: {by using masks}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07253: {changes in shapes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/224: {Bumps having multiple side-by-side cores}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/287: {Flow barriers}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 90/721: {of bump connectors}
- H10W 90/728: {between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Provided is a method of manufacturing a semiconductor device including a bump interconnect structure. In the method of manufacturing the semiconductor device, a first substrate including a connection pad is formed, and a bump including a solder layer and a metal post protruding from the solder layer are formed on the connection pad. A second substrate including a bump land may be formed. The first substrate may be disposed on the second substrate so that a protruding end of the metal post contacts the bump land, and the solder layer may be reflowed. Accordingly, it possible to interconnect the metal post to the bump land.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
forming a substrate including a connection pad;
forming a first resist pattern on the connection pad of the substrate, the first resist pattern including a ring-shaped first opening;
forming a ring pattern of a solder layer with an inserting hole by filling the ring-shaped first opening with a solder material;
selectively removing a portion of the first resist pattern that fills the inserting hole;
forming a second resist pattern with a second opening that substantially overlaps with the inserting hole; and
filling the second opening with a metal material to form a metal post, the metal post with an inserting portion that is inserted into the inserting hole and a protruding portion that protrudes outside of the ring pattern of the solder layer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising, before forming the first resist pattern, forming a seed metal layer that covers the connection pad of the substrate and extends onto the first substrate.

### Claim 3 (depends on 1)

The method of claim 1, wherein the solder layer is formed by plating the solder material.

### Claim 4 (depends on 1)

The method of claim 1, wherein the metal post is formed by plating the metal material.

### Claim 5 (depends on 1)

The method of claim 1, wherein selectively removing the portion of the first resist pattern that fills the inserting hole includes:
selectively irradiating an exposure light that is exposed to the portion of the first resist pattern that fills the inserting hole; and
developing the exposed portion of the first resist pattern.

### Claim 6

A method of manufacturing a semiconductor device, the method comprising:
forming a first substrate including a connection pad;
forming a bump on the connection pad, wherein the bump includes a solder layer and a metal post, and the solder layer has a ring pattern with an inserting hole, and wherein the metal post includes an inserting portion that is inserted into the inserting hole of the ring pattern and a protruding portion protruding out of the ring pattern;
forming a second substrate including a bump land;
disposing the first substrate over the second substrate such that the protruding end of the metal post contacts the bump land; and
reflowing the solder layer to interconnect the metal post to the bump land.

### Claim 7 (depends on 6)

The method of claim 6, wherein the reflowing of the solder layer is performed such that the solder layer flows down along a side surface of the metal post to form a side surface of the solder layer that is curved around the metal post.

### Claim 8 (depends on 6)

The method of claim 6,
wherein the bump land includes a concave groove, and
wherein the first substrate is disposed over the second substrate such that the protruding end of the metal post is inserted into the concave groove.

### Claim 9 (depends on 6)

The method of claim 6, wherein the solder layer includes tin (Sn), a tin-silver (SnAg) alloy, or a tin-silver-gold (AuSnAg) alloy.

### Claim 10 (depends on 6)

The method of claim 6, wherein the metal post includes copper (Cu).

### Claim 11 (depends on 6)

The method of claim 6, wherein the first substrate includes a semiconductor die.

### Claim 12 (depends on 11)

The method of claim 11, wherein the second substrate includes a packaging substrate on which the semiconductor die is mounted.

### Claim 13 (depends on 6)

The method of claim 6, wherein forming the bumps includes:
forming a first resist pattern on the connection pad of the first substrate, the first resist pattern including a ring-shaped first opening;
forming the solder layer in a ring pattern with an inserting hole by filling the ring-shaped first opening with a solder material;
selectively removing a portion that fills the inserting hole of the first resist pattern;
forming a second resist pattern with a second opening that substantially overlaps with the inserting hole; and
filling the second opening with a metal material to form the metal post.

### Claim 14 (depends on 13)

The method of claim 13, further comprising, before forming the first resist pattern, forming a seed metal layer that covers the connection pad of the first substrate and extends onto the first substrate.

### Claim 15 (depends on 13)

The method of claim 13, wherein the solder layer is formed by plating the solder material.

### Claim 16 (depends on 13)

The method of claim 13, wherein the metal post is formed by plating the metal material.

### Claim 17 (depends on 13)

The method of claim 13, wherein selectively removing the portion that fills the inserting hole of the first resist pattern includes:
selectively irradiating an exposure light that is exposed to a portion that fills the inserting hole of the first resist pattern; and
developing the exposed portion of the first resist pattern.

### Claim 18 (depends on 6)

The method of claim 6, wherein the solder layer is formed on the connection pad.

### Claim 19 (depends on 18)

The method of claim 18, wherein
the protruding portion extends from the inserting portion.

### Claim 20 (depends on 19)

The method of claim 19, wherein the reflowing of the solder layer includes the solder layer flowing down to cover at least a portion of a side surface of the protruding portion of the metal post to be bonded to the bump land.