# US 12,002,774 B2 · Passivation scheme for pad openings and trenches

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- Number: US 12,002,774 B2
- Document ID: US12002774B2
- Status: Granted
- Kind: B2
- Application number: 17/940,081
- Filed: 2022-09-08
- Published: 2023-01-05
- Granted: 2024-06-04
- Earliest claimed: 2017-07-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ming-Hong Chang; Chun-Yi Yang; Kun-Ming Huang; Po-Tao Chu; Shen-Ping Wang; Chien-Li Kuo
- Web page: https://patentgrep.com/patent/US12002774B2

## CPC

- H10W 20/43: Layouts of interconnections
- H10W 20/42: Vias, e.g. via plugs
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/90: Bond pads, in general
- H10W 74/10: characterised by their shape or disposition
- H10W 74/134: {the encapsulations being in grooves in the semiconductor body}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 72/019: {of bond pads}
- H10W 72/01953: {by etching}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 74/43: comprising oxides, nitrides or carbides, e.g. ceramics or glasses
- H10W 74/47: comprising organic materials, e.g. plastics or resins
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

## Claims

### Claim 1

An integrated circuit comprising:
a substrate;
an interlayer dielectric (ILD) layer overlying the substrate;
a conductive pad overlying the ILD layer; and
a passivation layer overlying the ILD layer and the conductive pad, and further lining a sidewall in a pad opening overlying and partially exposing the conductive pad, wherein the passivation layer has a curved portion.

### Claim 2 (depends on 1)

The integrated circuit according to claim 1, further comprising:
another passivation layer overlying the ILD layer and the conductive pad, wherein the other passivation layer defines the pad opening.

### Claim 3 (depends on 1)

The integrated circuit according to claim 1, wherein the ILD layer comprises oxide, and wherein the passivation layer comprises silicon nitride, aluminum oxide, or polyimide.

### Claim 4 (depends on 1)

The integrated circuit according to claim 1, wherein the passivation layer has an L-shaped profile directly contacting the conductive pad and the sidewall in the pad opening.

### Claim 5 (depends on 1)

The integrated circuit according to claim 1, further comprising:
another passivation layer overlying the passivation layer and lining a sidewall of the passivation layer in the pad opening.

### Claim 6 (depends on 5)

The integrated circuit according to claim 5, wherein the other passivation layer has a lower water vapor transmission rate than the ILD layer.

### Claim 7 (depends on 1)

The integrated circuit according to claim 1, further comprising:
a semiconductor device on the substrate; and
a conductive interconnect structure in the ILD layer and defining a conductive path from the semiconductor device to the conductive pad.

### Claim 8

An integrated circuit comprising:
a substrate;
an interlayer dielectric (ILD) layer overlying the substrate, wherein the ILD layer at least partially defines a trench, and wherein the trench extends vertically through the ILD layer from a top of the ILD layer to the substrate and further extends laterally in a closed path along an edge of the integrated circuit; and
a passivation layer overlying the ILD layer, wherein the passivation layer lines a sidewall of the ILD layer in the trench, and wherein the passivation layer has a curved portion.

### Claim 9 (depends on 8)

The integrated circuit according to claim 8, further comprising:
another passivation layer overlying the ILD layer, wherein the other passivation layer lines and directly contacts the sidewall of the ILD layer in the trench.

### Claim 10 (depends on 9)

The integrated circuit according to claim 9, further comprising:
a conductive pad overlying the ILD layer, wherein the passivation layer and the other passivation layer overlie the conductive pad, and wherein the passivation layer extends through the other passivation layer to the conductive pad at a pad opening overlying the conductive pad.

### Claim 11 (depends on 8)

The integrated circuit according to claim 8, wherein the passivation layer has a U-shaped or V-shaped profile in the trench.

### Claim 12 (depends on 8)

The integrated circuit according to claim 8, further comprising:
another passivation layer overlying the passivation layer, wherein the other passivation layer lines the sidewall of the ILD layer in the trench and over the passivation layer, and wherein the other passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

### Claim 13 (depends on 8)

The integrated circuit according to claim 8, further comprising:
a semiconductor device on the substrate and underlying the ILD layer, wherein the closed path surrounds the semiconductor device.

### Claim 14 (depends on 8)

The integrated circuit according to claim 8, wherein the substrate comprises a silicon layer and a group III-V layer overlying the silicon layer, and wherein the trench extends into the group III-V layer.

### Claim 15

An integrated circuit comprising:
a substrate;
a semiconductor device on the substrate;
an interlayer dielectric (ILD) layer overlying the semiconductor device;
a plurality of wires and a plurality of vias in the ILD layer, wherein the plurality of wires and the plurality of vias are alternatingly stacked over and define a conductive path leading from the semiconductor device; and
a passivation layer overlying the ILD layer, wherein the passivation layer lines a sidewall of the ILD layer in a trench at a periphery of the integrated circuit and further has a lower water vapor transmission rate than the ILD layer;
wherein the passivation layer at least partially defines a protrusion extending vertically to the substrate through the trench.

### Claim 16 (depends on 15)

The integrated circuit according to claim 15, wherein the protrusion is ring shaped and laterally surrounds the semiconductor device and the sidewall.

### Claim 17 (depends on 16)

The integrated circuit according to claim 16, wherein the passivation layer has a curved surface wrapping around a top corner of the ILD layer.

### Claim 18 (depends on 15)

The integrated circuit according to claim 15, further comprising:
another passivation layer overlying the wires and the vias, between the passivation layer and the ILD layer, wherein the other passivation layer has a curved surface facing and directly contacting the passivation layer, and wherein the protrusion is also partially defined by the other passivation layer.

### Claim 19 (depends on 15)

The integrated circuit according to claim 15, further comprising:
another passivation layer overlying the wires and the vias, between the passivation layer and the ILD layer; and
a metal structure underlying and directly contacting the other passivation layer at an interface, wherein the passivation layer seals the interface from vapor and/or moisture.

### Claim 20 (depends on 19)

The integrated circuit according to claim 19, wherein the passivation layer has a curved surface wrapping around a top corner of the metal structure.