# US 12,002,773 B2 · Hybrid pocket post and tailored via dielectric for 3D-integrated electrical device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,773 B2 - Document ID: US12002773B2 - Status: Granted - Kind: B2 - Application number: 17/190,850 - Filed: 2021-03-03 - Published: 2022-09-08 - Granted: 2024-06-04 - Earliest claimed: 2021-03-03 - Assignees: Raytheon Company - Applicants: Raytheon Company - Inventors: Andrew Clarke; Chad Fulk; Aaron M. Ramirez - Web page: https://patentgrep.com/patent/US12002773B2 ## CPC - H10F 39/811: {Interconnections} - H10F 77/93: {Interconnections} - H10F 39/184: {Infrared image sensors} - H10F 77/30: Coatings (arrangements for preventing damage to photovoltaic cells caused by corpuscular radiation H10F77/80) - H10F 77/933: {for devices having potential barriers} - H10W 90/00: Package configurations - H10F 30/10: the devices being sensitive to infrared radiation, visible or ultraviolet radiation, and having no potential barriers, e.g. photoresistors - H10F 77/1237: {having at least three elements, e.g. HgCdTe} - H10F 77/20: Electrodes - H10W 72/01351: {Changing the shapes of die-attach connectors} - H10W 72/01935: {by plating, e.g. electroless plating or electroplating} - H10W 72/01951: {Changing the shapes of bond pads} - H10W 72/01953: {by etching} - H10W 72/07236: {Soldering or alloying} - H10W 72/07331: {Connecting techniques} - H10W 72/344: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics} - H10W 72/90: Bond pads, in general - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/931: {Shapes of bond pads} - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/951: {Materials of bond pads} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 80/102: {Controlling the environment during the bonding, e.g. the temperature or pressure} - H10W 80/301: {Bonding techniques, e.g. hybrid bonding} - H10W 80/721: {having structure or size changed during the connecting} - H10W 80/732: {having shape changed during the connecting} - H10W 90/732: {between stacked chips} - H10W 90/792: {between multiple chips} - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An electrical device includes a substrate, an insulating layer supported by the substrate, and an electrically conductive vertical interconnect disposed in a via hole of the insulating layer. The insulating layer may be configured to provide a coefficient of thermal expansion (CTE) that is equal to or greater than a CTE of the vertical interconnect to thereby impart axial compressive forces at opposite ends of the interconnect. The vertical interconnect may be a hybrid interconnect structure including a low CTE conductor post having a pocket that contains a high CTE conductor contact. At low operating temperatures, the high CTE conductor contact is under tension due to the higher CTE, and thus the high CTE conductor contact relieves strain in the device by void expansion and elongation. ## Claims ### Claim 1 An electrical device comprising: a substrate; an insulating layer supported by the substrate, wherein the insulating layer has a via hole; and an electrically conductive vertical interconnect disposed in the via hole; wherein the vertical interconnect has a coefficient of thermal expansion that is equal to or less than a coefficient of thermal expansion of the insulating layer; and wherein the insulating layer is multilayered, including at least a first dielectric layer having a first coefficient of thermal expansion and a second dielectric layer having a second coefficient of thermal expansion, wherein the first coefficient of thermal expansion is greater than the second coefficient of thermal expansion, and wherein the coefficient of thermal expansion of the insulating layer is a combined coefficient of thermal expansion of at least the first and second coefficients of thermal expansion. ### Claim 2 (depends on 1) The electrical device according to claim 1, wherein the second dielectric layer is a bonding layer, and wherein the first dielectric layer at least partially underlies the bonding layer. ### Claim 3 (depends on 2) The electrical device according to claim 2, wherein the bonding layer is SiOx. ### Claim 4 (depends on 2) The electrical device according to claim 2, wherein the first dielectric layer is AlN or Al2O3. ### Claim 5 An electrical device comprising: a substrate; an insulating layer supported by the substrate, wherein the insulating layer has at a via hole; and an electrically conductive vertical interconnect disposed in the via hole; wherein the vertical interconnect has a coefficient of thermal expansion that is equal to or less than a coefficient of thermal expansion of the insulating layer; wherein the vertical interconnect includes a recessed cup in its upper surface; and wherein the recessed cup contains an electrically conductive contact having a coefficient of thermal expansion that is greater than the coefficient of thermal expansion of the vertical interconnect. ### Claim 6 (depends on 5) The electrical device according to claim 5, further comprising: a fragile material at least partially underlying the vertical interconnect, the fragile material having a KIC fracture toughness of less than 1 MPa·m1/2. ### Claim 7 (depends on 6) The electrical device according to claim 6, further comprising: an electrically conductive contact pad between the fragile material and the vertical interconnect for conducting electricity therebetween. ### Claim 8 (depends on 5) The electrical device according to claim 5, wherein the vertical interconnect includes polysilicon. ### Claim 9 (depends on 8) The electrical device according to claim 8, wherein the electrically conductive contact includes indium. ### Claim 10 (depends on 5) The electrical device according to claim 5, wherein the electrical device is a photoconductor, and wherein the substrate comprises mercury cadmium telluride overlying silicon. ### Claim 11 A 3D-integrated electrical device comprising a first electrical device bonded and electrically integrated to a second electrical device, each of the electrical devices including: a substrate; an insulating layer supported by the substrate, wherein the insulating layer has a via hole; and an electrically conductive vertical interconnect disposed in the via hole; wherein the vertical interconnect has a coefficient of thermal expansion that is equal to or less than a coefficient of thermal expansion of the insulating layer; the 3D-integrated electrical device comprising a hybrid vertical interconnect including: a post made with a first electrically conductive material of the electrically conductive vertical interconnects of the first electrical device and the second electrical device, and a contact disposed within a pocket of the post, the contact made with a second electrically conductive material, wherein the first electrically conductive material has a coefficient of thermal expansion that is less than a coefficient of thermal expansion of the second electrically conductive material. ### Claim 12 (depends on 11) The 3D-integrated electrical device according to claim 11, wherein the post is made of polysilicon, and wherein the contact is made of metal. ### Claim 13 (depends on 11) The 3D-integrated electrical device according to claim 11, wherein the first electrical device comprises a first insulating layer, wherein the second electrical device comprises a second insulating layer, and wherein the coefficient of thermal expansion of the post is equal to or less than respective coefficients of thermal expansion of the first and second insulating layers. ### Claim 14 (depends on 13) The 3D-integrated electrical device according to claim 13, wherein each of the first insulating layer and the second insulating layer includes a SiOx bonding layer and an AlN and/or Al2O3 dielectric layer, wherein the post includes polysilicon, and wherein the contact includes indium. ### Claim 15 (depends on 14) The 3D-integrated electrical device according to claim 14, wherein the first electrical device is a photodetector, and wherein the second electrical device is a read out integrated circuit.