# US 12,002,772 B2 · Semiconductor device with composite conductive features and method for fabricating the same

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- Number: US 12,002,772 B2
- Document ID: US12002772B2
- Status: Granted
- Kind: B2
- Application number: 17/698,545
- Filed: 2022-03-18
- Published: 2023-09-21
- Granted: 2024-06-04
- Earliest claimed: 2022-03-18
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Teng-Yen Huang
- Web page: https://patentgrep.com/patent/US12002772B2

## CPC

- H10W 90/00: Package configurations
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/01904: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01908: {using permanent auxiliary members, e.g. using alignment marks}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01951: {Changing the shapes of bond pads}
- H10W 72/01953: {by etching}
- H10W 72/921: {Structures or relative sizes of bond pads}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/936: {Multiple bond pads having different shapes}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/951: {Materials of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 72/963: {Providing mechanical bonding or support, e.g. dummy bond pads}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W 80/301: {Bonding techniques, e.g. hybrid bonding}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure and a first connecting structure, wherein the first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, two first conductive layers positioned in the first connecting insulating layer, and a first porous layer positioned between the two first conductive layers. A porosity of the first porous layer is between about 25% and about 100%. The first semiconductor structure includes a plurality of first composite conductive features, wherein at least one of the plurality of first composite conductive features includes a first protection liner, a first graphene liner in the first protection liner and a first core conductor in the first graphene liner.

## Claims

### Claim 1

A semiconductor device, comprising:
a first semiconductor structure comprising a plurality of first composite conductive features, wherein at least one of the plurality of first composite conductive features includes a first protection liner, a first graphene liner in the first protection liner and a first core conductor in the first graphene liner; and
a first connecting structure comprising a first connecting insulating layer positioned on the first semiconductor structure, two first conductive layers positioned in the first connecting insulating layer, and a first porous layer positioned between the two first conductive layers;
wherein a porosity of the first porous layer is between about 25% and about 100%.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first connecting insulating layer comprises a first bottom insulating layer positioned on the first semiconductor structure, and a first top insulating layer positioned on the first bottom insulating layer, wherein the two first conductive layers penetrate the first bottom insulating layer and the first top insulating layer, and the first porous layer penetrates the first top insulating layer and extends into the first bottom insulating layer.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the two first conductive layers comprise two first portions positioned on the first semiconductor structure and two second portions positioned on the first portions, wherein a width of the second portions is greater than a width of the first portions.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, further comprising a plurality of first top liners positioned on the first top insulating layer and surrounding the two second portions.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, further comprising a plurality of first bottom liners positioned between the plurality of first top liners and the first top insulating layer, between the two first conductive layers and the first top insulating layer, between the two first conductive layers and the first bottom insulating layer, between the first porous layer and the first top insulating layer, and between the first porous layer and the first bottom insulating layer.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein bottom surfaces of the plurality of first bottom liners are at a vertical level higher than a vertical level of a top surface of the first semiconductor structure.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, further comprising a plurality of barrier layers positioned between the two first conductive layers and the plurality of first top liners, between the two first conductive layers and the plurality of first bottom liners, between the two first conductive layers and the first top insulating layer, between the two first conductive layers and the first bottom insulating layer, and between the two first conductive layers and the first semiconductor structure.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein a width of the plurality of first conductive features is greater than a width of the first portions, and the first protection liner and the first graphene liner have a U-shaped profile.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, further comprising a second semiconductor structure positioned on the first connecting structure and comprising a plurality of second composite conductive features positioned on the second portions, wherein a width of the plurality of second composite conductive features is greater than the width of the second portions; at least one of the plurality of first composite conductive features includes a second protection liner, a second graphene liner in the second protection liner and a second core conductor in the second graphene liner; the second protection liner and the second graphene liner have a U-shaped profile.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, further comprising a third porous layer positioned between the plurality of first top liners and the second semiconductor structure and surrounding the second portions, wherein a porosity of the third porous layer is between about 25% and about 50%.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, further comprising a third porous layer positioned on the plurality of first top liners, and a fourth porous layer positioned between the third porous layer and the second semiconductor structure; wherein a porosity of the fourth porous layer is less than a porosity of the third porous layer.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the porosity of the third porous layer is between about 50% and about 85%.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein the second semiconductor structure comprises a plurality of guard rings positioned on the first connecting structure, and the first connecting structure comprises a plurality of first supporting layers positioned below the plurality of guard rings, wherein a thickness of the plurality of first supporting layers is less than a thickness of the two first conductive layers.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, further comprising a second connecting structure positioned between the first connecting structure and the second semiconductor structure, wherein the second connecting structure comprises two second conductive layers positioned between the two first conductive layers and the plurality of second composite conductive features, and a second porous layer positioned between the two second conductive layers, wherein a porosity of the second porous layer is between about 25% and about 100%.