# US 12,002,768 B2 · Semiconductor package and manufacturing method thereof

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- Number: US 12,002,768 B2
- Document ID: US12002768B2
- Status: Granted
- Kind: B2
- Application number: 17/458,607
- Filed: 2021-08-27
- Published: 2023-03-02
- Granted: 2024-06-04
- Earliest claimed: 2021-08-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yu-Chih Huang; Chih-Hao Chang; Po-Chun Lin; Chun-Ti Lu; Zheng-Gang Tsai; Shih-Wei Chen; Chia-Hung Liu; Hao-Yi Tsai; Chung-Shi Liu
- Web page: https://patentgrep.com/patent/US12002768B2

## CPC

- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10P 72/7418: {of passive members, e.g. a chip mounting substrate}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7434: {used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution structure, and conductive vias. The molded semiconductor device comprises a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input/output region and a sensing region at the first surface. The first redistribution structure is disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and the first redistribution structure comprises a conductive layer having a redistribution pattern and a ring structure. The redistribution pattern is electrically connected with the sensor die. The ring structure surrounds the sensing region and is separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern. The conductive vias extend through the molded semiconductor device and are electrically connected with the redistribution pattern.

## Claims

### Claim 1

A semiconductor package, comprising:
a molded semiconductor device comprising a sensor die, wherein the sensor die has a first surface and a second surface opposite the first surface, the sensor die has an input/output region and a sensing region at the first surface;
a first redistribution structure disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region of the sensor die and exposes the sensing region of the sensor die, and the first redistribution structure comprises a conductive layer having:
a redistribution pattern electrically connected with the sensor die; and
a ring structure surrounding the sensing region of sensor die and separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern, and the ring structure is electrically insulated from the sensor die; and
conductive vias extending through the molded semiconductor device and electrically connected with the redistribution pattern.

### Claim 2 (depends on 1)

The semiconductor package as claimed in claim 1, wherein the ring structure is located at the same level as the redistribution pattern.

### Claim 3 (depends on 1)

The semiconductor package as claimed in claim 1, wherein the sensor die comprises:
a semiconductor substrate;
pads disposed on the semiconductor substrate, wherein the pads are electrically connected with the redistribution pattern; and
a passivation film disposed on the pads and the semiconductor substrate.

### Claim 4 (depends on 3)

The semiconductor package as claimed in claim 3, wherein the ring structure contacts the passivation film.

### Claim 5 (depends on 1)

The semiconductor package as claimed in claim 1, further comprising:
a second redistribution structure disposed over the second surface of the sensor die, wherein the second redistribution structure is electrically connected with the conductive vias.

### Claim 6 (depends on 1)

The semiconductor package as claimed in claim 1, wherein the conductive layer further comprises:
a seal ring disposed on the molded semiconductor device, wherein the seal ring surrounds the redistribution pattern and the ring structure and is electrically isolated from the redistribution pattern and the ring structure.

### Claim 7

A semiconductor package, comprising:
a sensor die having a first surface and a second surface opposite the first surface, wherein the sensor die has a sensing region at the first surface;
an encapsulant at least laterally encapsulating the sensor die;
conductive vias penetrating through the encapsulant; and
a first redistribution structure disposed on the encapsulant and the first surface of the sensor die, and electrically connected with the sensor die and the conductive vias, wherein the first redistribution structure comprises:
a first dielectric layer and a second dielectric layer disposed on the first dielectric layer, wherein the first dielectric layer and the second dielectric layer define an opening exposing the sensing region of the sensor die; and
a ring structure sandwiched between the first dielectric layer and the second dielectric layer, extending through the first dielectric layer to be in contact with the first surface of the sensor die, and surrounding the opening, wherein the ring structure is electrically insulated from the sensor die.

### Claim 8 (depends on 7)

The semiconductor package as claimed in claim 7, wherein the first redistribution structure further comprises:
a redistribution pattern sandwiched between the first dielectric layer and the second dielectric layer, electrically connected with the sensor die and the conductive vias, and electrically insulated from the ring structure.

### Claim 9 (depends on 7)

The semiconductor package as claimed in claim 7, wherein the sensor die comprises:
a semiconductor substrate;
pads disposed on the semiconductor substrate, wherein the pads are electrically connected with the redistribution pattern; and
a passivation film disposed on the pads and the semiconductor substrate, and exposing portions of the pads.

### Claim 10 (depends on 9)

The semiconductor package as claimed in claim 9, wherein the ring structure is located between the opening and each of the pads.

### Claim 11 (depends on 9)

The semiconductor package as claimed in claim 9, wherein a topmost surface of the passivation film is below a topmost surface of the encapsulant.

### Claim 12 (depends on 9)

The semiconductor package as claimed in claim 9, wherein a topmost surface of the passivation film is above a topmost surface of the encapsulant.

### Claim 13 (depends on 9)

The semiconductor package as claimed in claim 9, wherein the ring structure is in contact with the passivation film.

### Claim 14 (depends on 7)

The semiconductor package as claimed in claim 7, further comprising:
a second redistribution structure disposed on the second surface of the sensor die, the second redistribution structure being electrically connected with the conductive vias.

### Claim 15 (depends on 7)

The semiconductor package as claimed in claim 7, wherein the first redistribution structure further comprises:
a seal ring disposed on the encapsulant, wherein the seal ring is sandwiched between the first dielectric layer and the second dielectric layer, surrounds the ring structure and is electrically insulated from the ring structure and the conductive vias.

### Claim 16

A manufacturing process for a semiconductor package, comprising:
providing a carrier;
forming conductive vias on the carrier;
placing a sensor die adjacent to the conductive vias, wherein the sensor die has a first surface and a second surface opposite the first surface, the sensor die has an input/output region and a sensing region at the first surface;
encapsulating the sensor die and the conductive vias with an encapsulant to form a molded semiconductor device, wherein the conductive vias extend through the molded semiconductor device; and
forming a first redistribution structure on the first surface of the sensor die, the conductive vias and the encapsulant, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and wherein forming the first redistribution structure comprises:
forming a conductive layer with a redistribution pattern electrically connected with the sensor die and the conductive vias, and a ring structure contacting the sensor die, surrounding the sensing region and separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern, and the ring structure is electrically insulated from the sensor die.

### Claim 17 (depends on 16)

The manufacturing process for the semiconductor package as claimed in claim 16, wherein the sensor die comprises:
a semiconductor substrate;
pads disposed on the semiconductor substrate, wherein the pads are electrically connected with the redistribution pattern; and
a passivation film disposed on the pads and the semiconductor substrate, and exposing portions of the pads.

### Claim 18 (depends on 17)

The manufacturing process for the semiconductor package as claimed in claim 17, wherein encapsulating the sensor die and the conductive vias comprises:
forming the encapsulant by compression molding process; and
planarizing the encapsulant such that top surfaces of the encapsulant and the conductive vias are above a top surface of the semiconductor substrate.

### Claim 19 (depends on 17)

The manufacturing process for the semiconductor package as claimed in claim 17, wherein encapsulating the sensor die and the conductive vias comprises:
forming the encapsulant by transfer molding process such that a recess in the encapsulant is disposed between the semiconductor substrate and the conductive vias.

### Claim 20 (depends on 17)

The manufacturing process for the semiconductor package as claimed in claim 17, wherein forming the first redistribution structure comprises:
forming a first dielectric layer on the encapsulant, the sensor die, and the conductive vias;
patterning the first dielectric layer with first openings exposing the conductive vias, second openings exposing the portions of the pads, a third opening exposing the sensing region of the sensor die, and a fourth opening;
forming the conductive layer extending through the first openings, the second openings and the third opening of the first dielectric layer to from the redistribution pattern and the ring structure, wherein the fourth opening of the first dielectric layer is free from the conductive layer;
forming a second dielectric layer on the conductive layer and the first dielectric layer; and
extending the fourth opening through the second dielectric layer to expose the sensing region of the sensor die.