# US 12,002,767 B2 · Integrated circuit package and method

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- Number: US 12,002,767 B2
- Document ID: US12002767B2
- Status: Granted
- Kind: B2
- Application number: 17/567,461
- Filed: 2022-01-03
- Published: 2022-04-21
- Granted: 2024-06-04
- Earliest claimed: 2018-11-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chung-Shi Liu; Jiun Yi Wu; Chien-Hsun Lee
- Web page: https://patentgrep.com/patent/US12002767B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/01: Manufacture or treatment
- H10W 74/014: {using batch processing}
- H10W 74/016: {using moulds}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/874: {On different surfaces}
- H10W 72/879: {Bump connectors and bond wires}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9413: {on encapsulations}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially encapsulating the integrated circuit die; a conductive via extending through the encapsulant; a redistribution structure on the encapsulant, the redistribution structure including: a metallization pattern electrically coupled to the conductive via and the integrated circuit die; a dielectric layer on the metallization pattern, the dielectric layer having a first thickness of 10 μm to 30 μm; and a first under-bump metallurgy (UBM) having a first via portion extending through the dielectric layer and a first bump portion on the dielectric layer, the first UBM being physically and electrically coupled to the metallization pattern, the first via portion having a first width, a ratio of the first thickness to the first width being from 1.33 to 1.66.

## Claims

### Claim 1

A device comprising:
an integrated circuit die;
an encapsulant at least partially encapsulating the integrated circuit die; and
a redistribution structure on the encapsulant, the redistribution structure comprising:
a metallization pattern electrically coupled to the integrated circuit die;
a dielectric layer on the metallization pattern; and
a first under-bump metallurgy (UBM) having a first via portion extending through the dielectric layer, a second via portion extending through the dielectric layer, and a bump portion on the dielectric layer, the first via portion and the second via portion contacting a same landing pad of the metallization pattern, the first via portion having a first width, the second via portion having a second width, the first width different from the second width, a difference between the first width and the second width being at least 5 μm.

### Claim 2 (depends on 1)

The device of claim 1, wherein the first via portion has a first thickness and the second via portion has a second thickness, a first ratio of the first thickness to the first width being from 1.33 to 1.66, a second ratio of the second thickness to the second width being from 1.33 to 1.66.

### Claim 3 (depends on 1)

The device of claim 1, wherein the bump portion, the first via portion, and the second via portion have a same shape in a top-down view.

### Claim 4 (depends on 1)

The device of claim 1, wherein the bump portion has a first shape in a top-down view, and the first via portion and the second via portion each have a second shape in the top-down view, the first shape being different from the second shape.

### Claim 5

A device comprising:
an integrated circuit die;
an encapsulant at least partially encapsulating the integrated circuit die; and
a redistribution structure on the encapsulant, the redistribution structure comprising:
a metallization pattern electrically coupled to the integrated circuit die;
a dielectric layer on the metallization pattern; and
a first under-bump metallurgy (UBM) having a first via portion extending through the dielectric layer, a second via portion extending through the dielectric layer, and a bump portion on the dielectric layer, the first via portion and the second via portion contacting a same landing pad of the metallization pattern, the bump portion having a first shape in a top-down view, the first via portion and the second via portion each have a second shape in the top-down view, the second shape being different from the first shape, wherein the first via portion has a first width and a first thickness, the second via portion has a second width and a second thickness, the first width is different from the second width, a first ratio of the first thickness to the first width is from 1.33 to 1.66, and a second ratio of the second thickness to the second width is from 1.33 to 1.66.

### Claim 6

A device comprising:
an integrated circuit die;
an encapsulant at least partially encapsulating the integrated circuit die; and
a redistribution structure on the encapsulant, the redistribution structure comprising:
a metallization pattern electrically coupled to the integrated circuit die;
a dielectric layer on the metallization pattern, the dielectric layer having a first thickness; and
a first under-bump metallurgy (UBM) having a first via portion extending through the dielectric layer, a second via portion extending through the dielectric layer, and a first bump portion on the dielectric layer, the first UBM being physically and electrically coupled to the metallization pattern, the first via portion having a first width, a ratio of the first thickness to the first width being from 1.33 to 1.66, the second via portion having a second width, a ratio of the first thickness to the second width being from 1.33 to 1.66.

### Claim 7 (depends on 6)

The device of claim 6, wherein the first bump portion has a third width, a ratio of the third width to the first width is at least 2.5, and a ratio of the third width to the second width is at least 2.5.

### Claim 8 (depends on 7)

The device of claim 7, wherein the third width is from 70 μm to 105 μm.

### Claim 9 (depends on 6)

The device of claim 6, wherein the first width and the second width are each from 20 μm to 25 μm.

### Claim 10 (depends on 6)

The device of claim 6, wherein the first bump portion has a second thickness, a ratio of the second thickness to the first thickness being at least 1.5.

### Claim 11 (depends on 10)

The device of claim 10, wherein the second thickness is from 10 μm to 40 μm.

### Claim 12 (depends on 10)

The device of claim 10, wherein the metallization pattern has a third thickness, and a ratio of the first thickness to the third thickness is at least 6.

### Claim 13 (depends on 12)

The device of claim 12, wherein the third thickness is from 0.8 μm to 4 μm.

### Claim 14 (depends on 6)

The device of claim 6, wherein a portion of the dielectric layer is between the first via portion and the second via portion of the first UBM, and the first via portion and the second via portion of the first UBM contact a same landing pad of the metallization pattern.

### Claim 15 (depends on 6)

The device of claim 6, wherein the second width is equal to the first width.

### Claim 16 (depends on 6)

The device of claim 6, wherein the second width is greater than the first width by at least 5 μm.

### Claim 17 (depends on 6)

The device of claim 6, wherein the first bump portion, the first via portion, and the second via portion of the first UBM have a same shape in a top-down view.

### Claim 18 (depends on 6)

The device of claim 6, wherein the first bump portion of the first UBM has a first shape in a top-down view, and the first via portion and the second via portion of the first UBM have a second shape in the top-down view, the first shape being different from the second shape.

### Claim 19 (depends on 6)

The device of claim 6, further comprising:
a conductive via extending through the encapsulant, the metallization pattern electrically coupled to the conductive via.

### Claim 20 (depends on 19)

The device of claim 19, wherein the first thickness is from 10 μm to 30 μm.