# US 12,002,763 B2 · Package substrate and semiconductor package including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,763 B2 - Document ID: US12002763B2 - Status: Granted - Kind: B2 - Application number: 18/081,900 - Filed: 2022-12-15 - Published: 2023-04-20 - Granted: 2024-06-04 - Earliest claimed: 2020-06-29 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Seungmin Kim - Web page: https://patentgrep.com/patent/US12002763B2 ## CPC - H10W 70/65: Shapes or dispositions of interconnections - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 70/611: {for connecting multiple chips together} - H10W 70/685: comprising multiple insulating layers - H10W 72/00: Interconnections or connectors in packages - H10W 90/00: Package configurations - H10W 72/07254: {changes in dispositions} - H10W 72/247: {Dispositions of multiple bumps} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/59: Bond pads specially adapted therefor - H10W 72/884: {Die-attach connectors and bond wires} - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/752: {between stacked chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A package substrate includes: a core insulation layer having first and second package regions and a boundary region between the first and second package regions; a first upper conductive pattern in the first package region; a second upper conductive pattern in the second package region; a first insulation pattern on the core insulation layer to partially expose the first and second upper conductive patterns, wherein the first insulation pattern includes a first trench at the boundary region, and first reinforcing portions in the first trench; a first lower conductive pattern in the first package region; a second lower conductive pattern in the second package region; and a second insulation pattern on the core insulation layer to partially expose the first and second lower conductive patterns, wherein the second insulation pattern includes a second trench at the boundary region, and second reinforcing portions in the second trench. ## Claims ### Claim 1 A package substrate comprising: a core insulation; an upper insulation pattern arranged on the core insulation layer, wherein the upper insulation pattern includes an upper trench; a lower insulation pattern arranged on the core insulation layer, wherein the lower insulation pattern includes a lower trench; and a reinforcing portion arranged in at least one of the upper trench or the lower trench. ### Claim 2 (depends on 1) The package substrate of claim 1, wherein the core insulation layer has at least two package regions and a boundary region between the at least two package regions, and the upper trench and the lower trench are formed at the boundary region. ### Claim 3 (depends on 2) The package substrate of claim 2, wherein the upper trench and the lower trench surround each of the at least two package regions. ### Claim 4 (depends on 2) The package substrate of claim 2, further comprising: upper conductive patterns arranged on the core insulation layer, the upper conductive patterns at least partially exposed through the upper insulation pattern; and lower conductive patterns arranged on the core insulation layer, the lower conductive patterns at least partially exposed through the lower insulation pattern. ### Claim 5 (depends on 4) The package substrate of claim 4, wherein the upper conductive patterns comprise: a first upper conductive pattern arranged on an upper surface of the core insulation layer in a first package region among the at least two package regions; and a second upper conductive pattern arranged on the upper surface of the core insulation layer in a second package region of the at least two package regions, wherein the second package region is adjacent to the first package region, and the second upper conductive pattern is electrically isolated from the first upper conductive pattern by the upper trench. ### Claim 6 (depends on 4) The package substrate of claim 4, wherein the lower conductive patterns comprise: a first lower conductive pattern arranged on a lower surface of the core insulation layer in a first package region among the at least two package regions; and a second lower conductive pattern arranged on the lower surface of the core insulation layer in a second package region of the at least two package regions, wherein the second package region is adjacent to the first package region, and the second lower conductive pattern is electrically isolated from the first lower conductive pattern by the lower trench. ### Claim 7 (depends on 1) The package substrate of claim 1, wherein the reinforcing portion is a part of at least one of the upper insulation pattern or the lower insulation pattern. ### Claim 8 (depends on 7) The package substrate of claim 7, wherein each of the upper insulation pattern and the lower insulation pattern comprises solder resist. ### Claim 9 (depends on 1) The package substrate of claim 1, wherein the reinforcing portion comprises: upper reinforcing portions overlapping the upper trench and positioned between a plurality of upper insulation holes configured to electrically isolate the upper conductive patterns from each other; and lower reinforcing portions overlapping the lower trench and positioned between a plurality of lower insulation holes configured to electrically isolate the lower conductive patterns from each other. ### Claim 10 (depends on 9) The package substrate of claim 9, wherein each of the upper reinforcing portions has a lower surface contacting an upper surface of the core insulation layer. ### Claim 11 (depends on 9) The package substrate of claim 9, wherein each of the lower reinforcing portions has an upper surface contacting a lower surface of the core insulation layer. ### Claim 12 (depends on 9) The package substrate of claim 9, wherein each of the upper reinforcing portions has a thickness of about 20% to about 80% of a thickness of the upper insulation pattern. ### Claim 13 (depends on 9) The package substrate of claim 9, wherein each of the lower reinforcing portions has a thickness of about 20% to about 80% of a thickness of the lower insulation pattern. ### Claim 14 A semiconductor package comprising: a package substrate including a core insulation layer, an upper insulation pattern, a lower insulation pattern and a reinforcing portion, wherein the upper insulation pattern is arranged on the core insulation layer, wherein the upper insulation pattern includes an upper trench, wherein the lower insulation pattern is arranged on the core insulation layer, wherein the lower insulation pattern includes a lower trench, and wherein the reinforcing portion is arranged in at least one of the upper trench or the lower trench; at least one semiconductor chip arranged on the package substrate; and a molding member arranged on the package substrate to cover the at least one semiconductor chip. ### Claim 15 (depends on 14) The semiconductor package of claim 14, wherein the core insulation layer has at least two package regions and a boundary region between the at least two package regions, and the upper trench and the lower trench are formed at the boundary region. ### Claim 16 (depends on 15) The semiconductor package of claim 15, further comprising: upper conductive patterns arranged on the core insulation layer, the upper conductive patterns at least partially exposed through the upper insulation pattern; and lower conductive patterns arranged on the core insulation layer, the lower conductive patterns at least partially exposed through the lower insulation pattern. ### Claim 17 (depends on 16) The semiconductor package of claim 16, wherein the upper conductive patterns comprise: a first upper conductive pattern arranged on an upper surface of the core insulation layer in a first package region among the at least two package regions; and a second upper conductive pattern arranged on the upper surface of the core insulation layer in a second package region of the at least two package regions, wherein the second package region is adjacent to the first package region, and the second upper conductive pattern is electrically isolated from the first upper conductive pattern by the upper trench. ### Claim 18 (depends on 16) The semiconductor package of claim 16, wherein the lower conductive patterns comprise: a first lower conductive pattern arranged on a lower surface of the core insulation layer in a first package region among the at least two package regions; and a second lower conductive pattern arranged on the lower surface of the core insulation layer in a second package region of the at least two package regions, wherein the second package region is adjacent to the first package region, and the second lower conductive pattern is electrically isolated from the first lower conductive pattern by the lower trench. ### Claim 19 (depends on 14) The semiconductor package of claim 14, wherein the reinforcing portion is a part of at least one of the upper insulation pattern or the lower insulation pattern. ### Claim 20 (depends on 14) The semiconductor package of claim 14, further comprising external terminals mounted on the package substrate and electrically connected with the lower conductive pattern.